/*
* Return 1 if executing on Intel, otherwise 0 (e.g., AMD64).
* Cache the result, as the CPU can't change.
*
* Note: the userland version uses getisax() and checks for an AMD-64-only
* feature. The kernel version uses cpuid_getvendor().
*/
int
arcfour_crypt_on_intel(void)
{
static int cached_result = -1;
if (cached_result == -1) { /* first time */
#ifdef _KERNEL
cached_result = (cpuid_getvendor(CPU) == X86_VENDOR_Intel);
#else
uint_t ui;
(void) getisax(&ui, 1);
cached_result = ((ui & AV_386_AMD_MMX) == 0);
#endif /* _KERNEL */
}
return (cached_result);
}
/*
* Set aes_present, des_present, digest_present and montmul_present
* to B_FALSE or B_TRUE depending on
* whether the current SPARC processor supports AES, DES,
* MD5/SHA1/SHA256/SHA512 and MONTMUL, respectively.
*/
static void
t4_instructions_present(_Bool *aes_present, _Bool *des_present,
_Bool *digest_present, _Bool *montmul_present)
{
#ifdef OPENSSL_NO_DES
#undef AV_SPARC_DES
#define AV_SPARC_DES 0
#endif
#ifdef OPENSSL_NO_MD5
#undef AV_SPARC_MD5
#define AV_SPARC_MD5 0
#endif
#ifndef OPENSSL_NO_SHA
#ifdef OPENSSL_NO_SHA1
#undef AV_SPARC_SHA1
#define AV_SPARC_SHA1 0
#endif
#ifdef OPENSSL_NO_SHA256
#undef AV_SPARC_SHA256
#define AV_SPARC_SHA256 0
#endif
#ifdef OPENSSL_NO_SHA512
#undef AV_SPARC_SHA512
#define AV_SPARC_SHA512 0
#endif
#else
#undef AV_SPARC_SHA1
#undef AV_SPARC_SHA256
#undef AV_SPARC_SHA512
#define AV_SPARC_SHA1 0
#define AV_SPARC_SHA256 0
#define AV_SPARC_SHA512 0
#endif /* !OPENSSL_NO_SHA */
#define DIGEST_MASK (AV_SPARC_MD5 | AV_SPARC_SHA1 | AV_SPARC_SHA256 | \
AV_SPARC_SHA512)
uint_t ui;
(void) getisax(&ui, 1);
*aes_present = ((ui & AV_SPARC_AES) != 0);
*des_present = ((ui & AV_SPARC_DES) != 0);
*digest_present = ((ui & DIGEST_MASK) == DIGEST_MASK);
*montmul_present = ((ui & AV_SPARC_MONT) != 0);
}
