void glcd_test_rectangles(void) { glcd_tiny_set_font(Font5x7,5,7,32,127); glcd_clear_buffer(); glcd_tiny_draw_string(0,0,"RECTANGLE DEMO"); glcd_write(); delay_ms(200); while(1) { glcd_clear(); glcd_draw_rect(0,0,100,50,BLACK); glcd_tiny_draw_string(0,GLCD_NUMBER_OF_BANKS-1,"glcd_draw_rect"); glcd_write(); delay_ms(500); DEMO_RETURN(); glcd_clear(); glcd_tiny_draw_string(0,GLCD_NUMBER_OF_BANKS-1,"glcd_draw_rect_thick"); glcd_write(); glcd_draw_rect_thick(5,5,80,30,3,6,BLACK); glcd_write(); delay_ms(500); DEMO_RETURN(); glcd_draw_rect_thick(0,0,20,20,2,2,BLACK); glcd_write(); delay_ms(500); DEMO_RETURN(); glcd_draw_rect_thick(100,10,20,20,5,5,BLACK); glcd_write(); delay_ms(500); DEMO_RETURN(); glcd_clear(); glcd_tiny_draw_string(0,GLCD_NUMBER_OF_BANKS-1,"glcd_draw_rect_shadow"); glcd_draw_rect_shadow(0,0,45,30,BLACK); glcd_write(); delay_ms(500); DEMO_RETURN(); glcd_draw_rect_shadow(95,5,30,30,BLACK); glcd_write(); delay_ms(500); DEMO_RETURN(); } }
void glcd_test_circles(void) { uint8_t x,y,radius; while (1) { uint8_t i; glcd_clear(); // generate random(ish) position on display x = rand() % GLCD_LCD_WIDTH; y = rand() % GLCD_LCD_HEIGHT; radius = rand() % 50; //x = 70; y=25; radius=50; // for debugging // fill circle with black for (i=0; i<=radius; i++) { glcd_fill_circle(x,y,i,BLACK); glcd_write(); delay_ms(2); } // fill the same circle above but with white for (i=0; i<=radius; i++) { glcd_fill_circle(x,y,i,WHITE); glcd_write(); delay_ms(1); } DEMO_RETURN(); } }
void InitialzeLCD(void){ sbi(DDR(LCD_BACKLIGHT_PORT),LCD_BACKLIGHT_PIN); //setting the LCD backlight pin and port sbi(LCD_BACKLIGHT_PORT,LCD_BACKLIGHT_PIN); glcd_init(); // initializes the LCD glcd_set_contrast(50); // sets constrast to default value glcd_clear(); // clears screen and buffer }
void glcd_power_down(void) { /* First, fill RAM with zeroes to ensure minimum specified current consumption */ glcd_clear(); /* Power down */ glcd_command(PCD8544_FUNCTION_SET|PCD8544_POWER_DOWN); }
void glcd_init(void) { /* Initialization of lib */ glcd_select_screen((uint8_t *)&glcd_buffer,&glcd_bbox); /* Initialization of device */ glcd_init_device(); glcd_clear(); }
void glcd_init(void) { #if defined(GLCD_CONTROLLER_PCD8544) /* * Set up SPI (SSP) * Note: Max allowed SPI clock is 4 MHz from datasheet. */ /* Select SSP/SPI port */ SSP_IOConfig( CONTROLLER_SPI_PORT_NUMBER ); /* Initialise SSP/SPI port */ SSP_Init( CONTROLLER_SPI_PORT_NUMBER ); /* Above functions take care of SPI pins */ /* Set SS, DC and RST pins to output */ CONTROLLER_SS_PORT->DIR |= (1 << CONTROLLER_SS_PIN); CONTROLLER_DC_PORT->DIR |= (1 << CONTROLLER_DC_PIN); CONTROLLER_RST_PORT->DIR |= (1 << CONTROLLER_RST_PIN); /* Deselect LCD */ //GLCD_DESELECT(); /* Reset the display */ glcd_reset(); /* Get into the EXTENDED mode! */ glcd_command(PCD8544_FUNCTION_SET | PCD8544_EXTENDED_INSTRUCTION); /* LCD bias select (4 is optimal?) */ glcd_command(PCD8544_SET_BIAS | 0x2); /* Set VOP */ glcd_command(PCD8544_SET_VOP | 50); // Experimentally determined /* Back to standard instructions */ glcd_command(PCD8544_FUNCTION_SET); /* Normal mode */ glcd_command(PCD8544_DISPLAY_CONTROL | PCD8544_DISPLAY_NORMAL); glcd_select_screen(glcd_buffer,&glcd_bbox); glcd_clear(); #else /* GLCD_CONTROLLER_PCD8544 */ #error "Controller not supported by LPC111x" #endif }
void glcd_init(void) { #if defined(GLCD_CONTROLLER_PCD8544) // Set up SPI (SSP) // Note: Max allowed SPI clock is 4 MHz from datasheet. // select SSP/SPI port SSP_IOConfig( PCD8544_SPI_PORT_NUMBER ); // initialise SSP/SPI port SSP_Init( PCD8544_SPI_PORT_NUMBER ); // above functions take care of SPI pins // set SS, DC and RST pins to output PCD8544_SS_PORT->DIR |= (1 << PCD8544_SS_PIN); PCD8544_DC_PORT->DIR |= (1 << PCD8544_DC_PIN); PCD8544_RST_PORT->DIR |= (1 << PCD8544_RST_PIN); // deselect LCD //GLCD_DESELECT(); // reset the display glcd_reset(); // get into the EXTENDED mode! glcd_command(PCD8544_FUNCTION_SET | PCD8544_EXTENDED_INSTRUCTION); // LCD bias select (4 is optimal?) glcd_command(PCD8544_SET_BIAS | 0x2); // set VOP glcd_command(PCD8544_SET_VOP | 50); // Experimentally determined // back to standard instructions glcd_command(PCD8544_FUNCTION_SET); // normal mode glcd_command(PCD8544_DISPLAY_CONTROL | PCD8544_DISPLAY_NORMAL); glcd_select_screen((uint8_t *)&glcd_buffer,&glcd_bbox); glcd_clear(); #else /* GLCD_CONTROLLER_PCD8544 */ #error Controller not supported. #endif }
void update_notes(int* notebuf, int* accidentalsbuf, int* octavebuf, int start, int buflen) { glcd_clear(); char line[15]; for (int i = start; i < ((start+24<buflen)?(start+24):buflen); i+=4) { sprintf(line, "%c%c%d%c%c%d%c%c%d%c%c%d", (char)(notebuf[i]+'A'), accidental_from_index(accidentalsbuf[i]), octavebuf[i], (char)(notebuf[i+1]+'A'), accidental_from_index(accidentalsbuf[i+1]), octavebuf[i+1], (char)(notebuf[i+2]+'A'), accidental_from_index(accidentalsbuf[i+2]), octavebuf[i+2], (char)(notebuf[i+3]+'A'), accidental_from_index(accidentalsbuf[i+3]), octavebuf[i+3]); glcd_draw_string_xy(0, (i-start)*2, line); } }
void glcd_test_scrolling_graph(void) { glcd_clear(); glcd_write(); while(1) { uint16_t n; for (n=0; n<=255; n += 20) { glcd_scrolling_bar_graph(0,0,50,50,n); glcd_scrolling_bar_graph(60,0,50,30,n); glcd_scrolling_bar_graph(60,35,60,20,n); DEMO_RETURN(); } for (n=0; n<=255; n += 20) { glcd_scrolling_bar_graph(0,0,50,50,255-n); glcd_scrolling_bar_graph(60,0,50,30,n); glcd_scrolling_bar_graph(60,35,60,20,n); DEMO_RETURN(); } } }
int main(void) { uint32_t color=0,i=0; LED_GPIO_Config(); glcd_init(); glcd_clear(BLUE); //timer_init(); glcd_set_colors(RED,BLUE); delay_ms(50); glcd_draw_hline(100,100,100); glcd_draw_hline(100,200,100); glcd_draw_vline(100,100,100); glcd_draw_vline(200,100,100); glcd_draw_string(1,1,"Hello My LCD"); glcd_draw_num(10,50,12345,5); delay_ms(50); glcd_set_colors(RED,GREEN); delay_ms(50); glcd_draw_circle(200,100,50); delay_ms(50); glcd_fill_circle(100,100,50); delay_ms(50); glcd_draw_rect(300,50,100,80); delay_ms(50); glcd_fill_rect(300,150,100,80); while (1) { debug("hello,I am xiaonong! This is line %d\r\n",++i); delay_ms(500); LED1(OFF); delay_ms(500); LED1(ON); // color = rand()%0xffffffff; // glcd_clear(color); } }
void glcd_init(void) { #if defined(GLCD_CONTROLLER_PCD8544) /* Set pin directions */ /* * Set up SPI for AVR8 * Note: AVR's SS pin must be set to output, regardless of whether we * actually use it. This is a requirement of SPI mster mode. */ sbi(DDR(AVR_SS_PORT),AVR_SS_PIN); /* * Set MOSI, Master SS, SCK to output (otherwise SPI won't work) * Must be done even if native SS pin not used */ sbi(DDR(CONTROLLER_MOSI_PORT),CONTROLLER_MOSI_PIN); sbi(DDR(CONTROLLER_SS_PORT),CONTROLLER_SS_PIN); sbi(DDR(CONTROLLER_SCK_PORT),CONTROLLER_SCK_PIN); /* Set SS, DC and RST pins to output */ sbi( DDR(CONTROLLER_SS_PORT), CONTROLLER_SS_PIN ); sbi( DDR(CONTROLLER_DC_PORT), CONTROLLER_DC_PIN ); sbi( DDR(CONTROLLER_RST_PORT), CONTROLLER_RST_PIN ); /* Deselect LCD */ GLCD_DESELECT(); /* * Max allowed SPI clock is 4 MHz from datasheet. * Enable SPI, set master mode and clock rate to /4 (4MHz with F_CPU=8MHz) */ SPCR = (1<<SPE)|(1<<MSTR); SPSR = 0; glcd_reset(); /* Get into the EXTENDED mode! */ glcd_command(PCD8544_FUNCTION_SET | PCD8544_EXTENDED_INSTRUCTION); /* LCD bias select (4 is optimal?) */ glcd_command(PCD8544_SET_BIAS | 0x2); /* Set VOP */ glcd_command(PCD8544_SET_VOP | 50); // Experimentally determined /* Back to standard instructions */ glcd_command(PCD8544_FUNCTION_SET); /* Normal mode */ glcd_command(PCD8544_DISPLAY_CONTROL | PCD8544_DISPLAY_NORMAL); /* Select screen buffer */ glcd_select_screen(glcd_buffer,&glcd_bbox); /* Clear screen, we are now ready to go */ glcd_clear(); #elif defined(GLCD_CONTROLLER_ST7565R) /* Set up GPIO directions */ /* * Set up SPI for AVR8 * Note: AVR's SS pin must be set to output, regardless of whether we * actually use it. This is a requirement of SPI mster mode. */ sbi(DDR(AVR_SS_PORT),AVR_SS_PIN); /* Set SCK and MOSI as output */ sbi(DDR(CONTROLLER_SCK_PORT),CONTROLLER_SCK_PIN); sbi(DDR(CONTROLLER_MOSI_PORT),CONTROLLER_MOSI_PIN); /* * Set MISO as input with pullup. This needs to be set for * SPI to work, even though we never use or read it. */ cbi(DDR(CONTROLLER_MISO_PORT),CONTROLLER_MISO_PIN); // B3 MISO as input sbi(CONTROLLER_MISO_PORT,CONTROLLER_MISO_PIN); /* Set pin to controller SS as output */ sbi(DDR(CONTROLLER_SS_PORT),CONTROLLER_SS_PIN); // A5 /* Set LCD A0 pin as output */ sbi(DDR(CONTROLLER_A0_PORT),CONTROLLER_A0_PIN); // A6 /* Init SS pin high (i.e LCD deselected) */ sbi(CONTROLLER_SS_PORT,CONTROLLER_SS_PIN); /* Deselect LCD */ GLCD_DESELECT(); /* MSB first, double speed, SPI mode 0 */ SPCR = (1<<SPE) | (1<<MSTR) | (0<<CPOL) | (0<<CPHA); sbi(SPSR,SPI2X); /* Enable interrupts */ sei(); delay_ms(30); // example in datasheet does this (20ms) glcd_command(ST7565R_RESET); // internal reset glcd_command(0xa2); // 1/9 bias glcd_command(0xa0); // ADC select, normal glcd_command(0xc8); // com output reverse glcd_command(0xa4); // display all points normal glcd_command(0x40); // display start line set glcd_command(0x25); // internal resistor ratio glcd_command(0x81); // electronic volume mode set //glcd_command(0x10); // electronic volume - datasheet's contrast example doesn't work glcd_command(45); // this works better glcd_command(0x2f); // power controller set glcd_command(0xaf); // display on glcd_all_on();
void glcd_init(void) { #if defined(GLCD_CONTROLLER_PCD8544) /* * Set up SPI (SSP) * Note: Max allowed SPI clock is 4 MHz from datasheet. */ /* Select SSP/SPI port */ SSP_IOConfig( CONTROLLER_SPI_PORT_NUMBER ); /* Initialise SSP/SPI port */ SSP_Init( CONTROLLER_SPI_PORT_NUMBER ); /* Above functions take care of SPI pins */ /* Set SS, DC and RST pins to output */ CONTROLLER_SS_PORT->DIR |= (1 << CONTROLLER_SS_PIN); CONTROLLER_DC_PORT->DIR |= (1 << CONTROLLER_DC_PIN); CONTROLLER_RST_PORT->DIR |= (1 << CONTROLLER_RST_PIN); /* Deselect LCD */ GLCD_DESELECT(); /* Reset the display */ glcd_reset(); /* Get into the EXTENDED mode! */ glcd_command(PCD8544_FUNCTION_SET | PCD8544_EXTENDED_INSTRUCTION); /* LCD bias select (4 is optimal?) */ glcd_command(PCD8544_SET_BIAS | 0x2); /* Set VOP */ glcd_command(PCD8544_SET_VOP | 50); // Experimentally determined /* Back to standard instructions */ glcd_command(PCD8544_FUNCTION_SET); /* Normal mode */ glcd_command(PCD8544_DISPLAY_CONTROL | PCD8544_DISPLAY_NORMAL); glcd_select_screen(glcd_buffer,&glcd_bbox); glcd_clear(); #elif defined(GLCD_CONTROLLER_NT75451) /* Parallel interface controller used on NGX BlueBoards */ /* Set 4x control lines pins as output */ LPC_GPIO->DIR[CONTROLLER_LCD_EN_PORT] |= (1U<<CONTROLLER_LCD_EN_PIN); LPC_GPIO->DIR[CONTROLLER_LCD_RW_PORT] |= (1U<<CONTROLLER_LCD_RW_PIN); LPC_GPIO->DIR[CONTROLLER_LCD_RS_PORT] |= (1U<<CONTROLLER_LCD_RS_PIN); LPC_GPIO->DIR[CONTROLLER_LCD_CS_PORT] |= (1U<<CONTROLLER_LCD_CS_PIN); /* Don't worry about setting default RS/RW/CS/EN, they get set during use */ #ifdef CONTROLLER_LCD_DATA_PORT /* Set data pins as output */ LPC_GPIO->DIR[CONTROLLER_LCD_D0_PORT] |= GLCD_PARALLEL_MASK; #else #error "Support of parallel data pins on different ports not supported." #endif /* Initialise sequence - code by NGX Technologies */ glcd_command(0xE2); /* S/W RESWT */ glcd_command(0xA0); /* ADC select */ glcd_command(0xC8); /* SHL Normal */ glcd_command(0xA3); /* LCD bias */ glcd_command(0x2F); /* Power control */ glcd_command(0x22); /* reg resistor select */ glcd_command(0x40); /* Initial display line 40 */ glcd_command(0xA4); /* Normal display */ glcd_command(0xA6); /* Reverce display a7 */ glcd_command(0x81); /* Ref vg select mode */ glcd_command(0x3f); /* Ref vg reg select */ glcd_command(0xB0); /* Set page address */ glcd_command(0x10); /* Set coloumn addr MSB */ glcd_command(0x00); /* Set coloumn addr LSB */ glcd_command(0xAF); /* Display ON */ /* Select default screen buffer */ glcd_select_screen(glcd_buffer,&glcd_bbox); /* Clear the screen buffer */ glcd_clear(); #else /* GLCD_CONTROLLER_PCD8544 */ #error "Controller not supported by LPC111x" #endif }
/************************************************************************************************************** * 函数名:glcd_init() * 输入 :void * 输出 :void * 描述 :LCD初始化函数 * 调用 :外部调用 *****************************************************************************************************************/ void glcd_init(void ) { glcd_gpio_config(); /* 2. 初始化display controller * 2.1 hsync,vsync,vclk,vden的极性和时间参数 * 2.2 行数、列数(分辨率),象素颜色的格式 * 2.3 分配显存(frame buffer),写入display controller */ LCDCON1 = IMAP_LCDCON1_PNRMODE_TFTLCD | IMAP_LCDCON1_ENVID_DISABLE |IMAP_LCDCON1_CLKVAL(LCD_CLK_DIV); LCDCON2 = IMAP_LCDCON2_VBPD(LCD_VBP - 1) | IMAP_LCDCON2_LINEVAL(LCD_VRES - 1) | IMAP_LCDCON2_VFPD(LCD_VFP - 1) | IMAP_LCDCON2_VSPW(LCD_VSW - 1); LCDCON3 = IMAP_LCDCON3_HBPD(LCD_HBP - 1) | IMAP_LCDCON3_HOZVAL(LCD_HRES - 1) | IMAP_LCDCON3_HFPD(LCD_HFP - 1); LCDCON4 = IMAP_LCDCON4_HSPW(LCD_HSW - 1); LCDCON5 = (LCD_RGB << 24) | IMAP_LCDCON5_INVVCLK_FALLING_EDGE | IMAP_LCDCON5_INVVLINE_INVERTED | IMAP_LCDCON5_INVVFRAME_INVERTED | IMAP_LCDCON5_INVVD_NORMAL| IMAP_LCDCON5_INVVDEN_NORMAL | IMAP_LCDCON5_INVPWREN_NORMAL | IMAP_LCDCON5_PWREN_ENABLE; OVCDCR = IMAP_OVCDCR_IFTYPE_RGB, #if defined (CONFIG_LCD_BPP8) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_8BPP_ARGB232 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_8BPP_ARGB232 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_8BPP_ARGB232 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_8BPP_ARGB232 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP16) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_16BPP_RGB565 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_16BPP_RGB565 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_16BPP_RGB565 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_16BPP_RGB565 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP18) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_18BPP_RGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_18BPP_RGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_18BPP_RGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_18BPP_RGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP19) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_19BPP_ARGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_19BPP_ARGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_19BPP_ARGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_19BPP_ARGB666 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP24) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_24BPP_RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_24BPP_RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_24BPP_RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_24BPP_RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP25) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_25BPP_ARGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_25BPP_ARGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_25BPP_ARGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_25BPP_ARGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP28) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_28BPP_A4RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_28BPP_A4RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_28BPP_A4RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_28BPP_A4RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; #elif defined (CONFIG_LCD_BPP32) OVCW0CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_BPPMODE_32BPP_A8RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW1CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_32BPP_A8RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW2CR = IMAP_OVCWxCR_BUFSEL_BUF0 | IMAP_OVCWxCR_BUFAUTOEN_DISABLE | IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_32BPP_A8RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; OVCW3CR = IMAP_OVCWxCR_BITSWP_DISABLE | IMAP_OVCWxCR_BIT2SWP_DISABLE | IMAP_OVCWxCR_BIT4SWP_DISABLE | IMAP_OVCWxCR_BYTSWP_DISABLE | IMAP_OVCWxCR_HAWSWP_DISABLE | IMAP_OVCWxCR_ALPHA_SEL_1 | IMAP_OVCWxCR_BLD_PIX_PLANE | IMAP_OVCWxCR_BPPMODE_32BPP_A8RGB888 | IMAP_OVCWxCR_ENWIN_DISABLE; #endif OVCW0PCAR = IMAP_OVCWxPCAR_LEFTTOPX(0) | IMAP_OVCWxPCAR_LEFTTOPY(0), OVCW0PCBR = IMAP_OVCWxPCBR_RIGHTBOTX(LCD_HRES_OSD - 1) | IMAP_OVCWxPCBR_RIGHTBOTY(LCD_VRES_OSD - 1), OVCW0CMR = IMAP_OVCWxCMR_MAPCOLEN_DISABLE, #if (CONFIG_FB_IMAP_NUM > 1) OVCW1PCAR = IMAP_OVCWxPCAR_LEFTTOPX(0) | IMAP_OVCWxPCAR_LEFTTOPY(0), OVCW1PCBR = IMAP_OVCWxPCBR_RIGHTBOTX(IMAPFB_HRES_OSD - 1) | IMAP_OVCWxPCBR_RIGHTBOTY(IMAPFB_VRES_OSD - 1), OVCW1PCCR = IMAP_OVCWxPCCR_ALPHA0_R(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA0_G(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA0_B(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_R(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_G(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_B(IMAPFB_MAX_ALPHA_LEVEL), OVCW1CMR = IMAP_OVCWxCMR_MAPCOLEN_DISABLE, #endif #if (CONFIG_FB_IMAP_NUM > 2) OVCW2PCAR = IMAP_OVCWxPCAR_LEFTTOPX(0) | IMAP_OVCWxPCAR_LEFTTOPY(0), OVCW2PCBR = IMAP_OVCWxPCBR_RIGHTBOTX(IMAPFB_HRES_OSD - 1) | IMAP_OVCWxPCBR_RIGHTBOTY(IMAPFB_VRES_OSD - 1), OVCW2PCCR = IMAP_OVCWxPCCR_ALPHA0_R(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA0_G(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA0_B(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_R(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_G(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_B(IMAPFB_MAX_ALPHA_LEVEL), OVCW2CMR = IMAP_OVCWxCMR_MAPCOLEN_DISABLE, #endif #if (CONFIG_FB_IMAP_NUM > 3) OVCW3PCAR = IMAP_OVCWxPCAR_LEFTTOPX(0) | IMAP_OVCWxPCAR_LEFTTOPY(0), OVCW3PCBR = IMAP_OVCWxPCBR_RIGHTBOTX(IMAPFB_HRES_OSD - 1) | IMAP_OVCWxPCBR_RIGHTBOTY(IMAPFB_VRES_OSD - 1), OVCW3PCCR = IMAP_OVCWxPCCR_ALPHA0_R(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA0_G(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA0_B(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_R(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_G(IMAPFB_MAX_ALPHA_LEVEL) | IMAP_OVCWxPCCR_ALPHA1_B(IMAPFB_MAX_ALPHA_LEVEL), OVCW3CMR = IMAP_OVCWxCMR_MAPCOLEN_DISABLE, #endif //选择window0的BUF0,使用两个BUF,使用24BPP_RGB888模式 OVCW0CR=IMAP_OVCWxCR_BUFSEL_BUF0|IMAP_OVCWxCR_BUFNUM_2BUFS |IMAP_OVCWxCR_BPPMODE_24BPP_RGB888; //设置window0的BUF0的framebuffer地址 OVCW0B0SAR =FRAME_BUFFER; glcd_clear(BLUE); glcd_display_on(); }
int main() { int noteBuffer[SONG_SIZE]; int accidentals[SONG_SIZE]; int octaveBuffer[SONG_SIZE]; memcpy(noteBuffer, rom_notes, SONG_SIZE*sizeof(int)); memcpy(accidentals, rom_accidentals, SONG_SIZE*sizeof(int)); memcpy(octaveBuffer, rom_octaves, SONG_SIZE*sizeof(int)); const int buf_size = SONG_SIZE; //uint8 selected; initHardware(); int start = 0; while (1) { //glcd_clear(); glcd_tiny_set_font(Font5x7,5,7,32,127); update_notes(noteBuffer, accidentals, octaveBuffer, start, buf_size); if (start > 0) { glcd_draw_string_xy(13*6,0,"^"); } if (start+4 < buf_size) { glcd_draw_string_xy(13*6,5*8,"v"); } glcd_draw_char_xy(13*6,1*8,(start/4+1)/100%10+'0'); glcd_draw_char_xy(13*6,2*8,(start/4+1)/10%10+'0'); glcd_draw_char_xy(13*6,3*8,(start/4+1)%10+'0'); glcd_write(); /* start+=4; if (start > 24) start = 0; */ int reading = 0; not_scroll: reading = Keypad_1_GetButton(); switch (reading) { case 7: if (start+4 < buf_size) start+=4; break; case 15: if (start > 0) start-=4; break; case 3: play_song(noteBuffer, accidentals, octaveBuffer, buf_size); break; case 0: for (int i = 0; i < 4; ++i) { glcd_invert_area(i*18, 0, 6, 8); glcd_write(); CyDelay(200); int button = 7; while (button > 6) { button = keycode_to_note[Keypad_1_GetButton()]; } noteBuffer[start+i] = button; update_notes(noteBuffer, accidentals, octaveBuffer, start, buf_size); glcd_invert_area(i*18+6, 0, 6, 8); glcd_write(); CyDelay(200); button = 2; while (button > 1) { button = keycode_to_accidental[Keypad_1_GetButton()]; if (button == 99) goto cancel_edit; } accidentals[start+i] = button; update_notes(noteBuffer, accidentals, octaveBuffer, start, buf_size); glcd_invert_area(i*18+12, 0, 6, 8); glcd_write(); CyDelay(200); button = 10; while (button > 9) { button = keycode_to_octave[Keypad_1_GetButton()]; if (button == 99) goto cancel_edit; } octaveBuffer[start+i] = button; update_notes(noteBuffer, accidentals, octaveBuffer, start, buf_size); } cancel_edit: break; case 1: glcd_clear(); glcd_draw_string_xy(0,0,"Saving..."); glcd_write(); int fail = 0; fail += CYRET_SUCCESS!=Em_EEPROM_Write((void*)noteBuffer, (void*)rom_notes, SONG_SIZE*sizeof(int)); fail += CYRET_SUCCESS!=Em_EEPROM_Write((void*)accidentals, (void*)rom_accidentals, SONG_SIZE*sizeof(int)); fail += CYRET_SUCCESS!=Em_EEPROM_Write((void*)octaveBuffer, (void*)rom_octaves, SONG_SIZE*sizeof(int)); if (fail) { glcd_draw_string_xy(0,8,"Failed!"); glcd_write(); CyDelay(1000); } else { glcd_draw_string_xy(0,8,"Success!"); glcd_write(); CyDelay(300); } break; default: goto not_scroll; } CyDelay(50); } }
void glcd_init(void) { #if defined(GLCD_CONTROLLER_PCD8544) /* Set pin directions */ /* * Set up SPI for AVR8 * Note: AVR's SS pin must be set to output, regardless of whether we * actually use it. This is a requirement of SPI mster mode. */ sbi(DDR(AVR_SS_PORT),AVR_SS_PIN); /* * Set MOSI, Master SS, SCK to output (otherwise SPI won't work) * Must be done even if native SS pin not used */ sbi(DDR(CONTROLLER_MOSI_PORT),CONTROLLER_MOSI_PIN); sbi(DDR(CONTROLLER_SS_PORT),CONTROLLER_SS_PIN); sbi(DDR(CONTROLLER_SCK_PORT),CONTROLLER_SCK_PIN); /* Set SS, DC and RST pins to output */ sbi( DDR(CONTROLLER_SS_PORT), CONTROLLER_SS_PIN ); sbi( DDR(CONTROLLER_DC_PORT), CONTROLLER_DC_PIN ); sbi( DDR(CONTROLLER_RST_PORT), CONTROLLER_RST_PIN ); /* Deselect LCD */ GLCD_DESELECT(); /* * Max allowed SPI clock is 4 MHz from datasheet. * Enable SPI, set master mode and clock rate to /4 (4MHz with F_CPU=8MHz) */ SPCR = (1<<SPE)|(1<<MSTR); SPSR = 0; glcd_PCD8544_init(); /* Select screen buffer */ glcd_select_screen(glcd_buffer,&glcd_bbox); /* Clear screen, we are now ready to go */ glcd_clear(); #elif defined(GLCD_CONTROLLER_ST7565R) /* Set up GPIO directions */ /* * Set up SPI for AVR8 * Note: AVR's SS pin must be set to output, regardless of whether we * actually use it. This is a requirement of SPI mster mode. */ sbi(DDR(AVR_SS_PORT),AVR_SS_PIN); /* Set SCK and MOSI as output */ sbi(DDR(CONTROLLER_SCK_PORT),CONTROLLER_SCK_PIN); sbi(DDR(CONTROLLER_MOSI_PORT),CONTROLLER_MOSI_PIN); /* * Set MISO as input with pullup. This needs to be set for * SPI to work, even though we never use or read it. */ cbi(DDR(CONTROLLER_MISO_PORT),CONTROLLER_MISO_PIN); // B3 MISO as input sbi(CONTROLLER_MISO_PORT,CONTROLLER_MISO_PIN); /* Set pin to controller SS as output */ sbi(DDR(CONTROLLER_SS_PORT),CONTROLLER_SS_PIN); // A5 /* Set LCD A0 pin as output */ sbi(DDR(CONTROLLER_A0_PORT),CONTROLLER_A0_PIN); // A6 /* Init SS pin high (i.e LCD deselected) */ sbi(CONTROLLER_SS_PORT,CONTROLLER_SS_PIN); /* Deselect LCD */ GLCD_DESELECT(); /* MSB first, double speed, SPI mode 0 */ SPCR = (1<<SPE) | (1<<MSTR) | (0<<CPOL) | (0<<CPHA); sbi(SPSR,SPI2X); /* Enable interrupts */ sei(); delay_ms(30); /* Example in datasheet does this (20ms) */ glcd_ST7565R_init(); glcd_all_on(); delay_ms(500); glcd_normal(); glcd_set_start_line(0); glcd_clear_now(); glcd_select_screen(glcd_buffer,&glcd_bbox); glcd_clear(); #else #error "Controller not supported" #endif /* GLCD_CONTROLLER_* */ }
void glcd_init(void) { #if defined(GLCD_CONTROLLER_PCD8544) /* Initialisation for PCD8544 controller */ /* Declare GPIO and SPI init structures */ GPIO_InitTypeDef GPIO_InitStructure; SPI_InitTypeDef SPI_InitStructure; //NVIC_InitTypeDef NVIC_InitStructure; /* Initialise structures (which we will overide later) */ GPIO_StructInit(&GPIO_InitStructure); SPI_StructInit(&SPI_InitStructure); /* Need to make start up the correct peripheral clocks */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE); /* SS pin */ GPIO_InitStructure.GPIO_Pin = CONTROLLER_SPI_SS_PIN; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_3; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_Init(CONTROLLER_SPI_SS_PORT, &GPIO_InitStructure); /* DC pin */ GPIO_InitStructure.GPIO_Pin = CONTROLLER_SPI_DC_PIN; GPIO_Init(CONTROLLER_SPI_DC_PORT, &GPIO_InitStructure); /* RESET pin */ GPIO_InitStructure.GPIO_Pin = CONTROLLER_SPI_RST_PIN; GPIO_Init(CONTROLLER_SPI_RST_PORT, &GPIO_InitStructure); /* Make sure chip is de-selected by default */ GLCD_DESELECT(); /* Set up GPIO for SPI pins */ GPIO_InitStructure.GPIO_Pin = CONTROLLER_SPI_SCK_PIN | CONTROLLER_SPI_MISO_PIN | CONTROLLER_SPI_MOSI_PIN; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_Level_3; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_Init(CONTROLLER_SPI_PORT, &GPIO_InitStructure); /* Configure alternate function mode for SPI pins */ GPIO_PinAFConfig(GPIOA,CONTROLLER_SPI_SCK_PINSRC,GPIO_AF_0); GPIO_PinAFConfig(GPIOA,CONTROLLER_SPI_MOSI_PINSRC,GPIO_AF_0); GPIO_PinAFConfig(GPIOA,CONTROLLER_SPI_MISO_PINSRC,GPIO_AF_0); /* Initialise SPI */ SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; SPI_InitStructure.SPI_Mode = SPI_Mode_Master; SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32; /* Set clock speed! */ SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; SPI_InitStructure.SPI_CRCPolynomial = 7; SPI_Init(CONTROLLER_SPI_NUMBER, &SPI_InitStructure); /* Enable SPI interupts */ /* SPI_I2S_ITConfig(CONTROLLER_SPI_NUMBER, SPI_I2S_IT_TXE, ENABLE); NVIC_InitStructure.NVIC_IRQChannel = SPI1_IRQn; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_InitStructure.NVIC_IRQChannelPriority = 0x00; NVIC_Init(&NVIC_InitStructure); */ /* Enable SPI */ SPI_Cmd(CONTROLLER_SPI_NUMBER, ENABLE); /* Initialisation sequence of controller */ glcd_reset(); /* Get into the EXTENDED mode! */ glcd_command(PCD8544_FUNCTION_SET | PCD8544_EXTENDED_INSTRUCTION); /* LCD bias select (4 is optimal?) */ glcd_command(PCD8544_SET_BIAS | 0x2); /* Set VOP */ glcd_command(PCD8544_SET_VOP | 50); // Experimentally determined /* Back to standard instructions */ glcd_command(PCD8544_FUNCTION_SET); /* Normal mode */ glcd_command(PCD8544_DISPLAY_CONTROL | PCD8544_DISPLAY_NORMAL); glcd_select_screen((uint8_t *)&glcd_buffer,&glcd_bbox); glcd_set_contrast(50); glcd_clear(); #else #error "Controller not supported by STM32F0xx" #endif }
int main(void) { /*Se inicializan los puertos. */ DDRB=0x00; DDRA= 0xFF; DDRC=0xff; /*Se inicializan los puertos que generan las interupciones externas */ DDRD= 0x00; DDRE=0x00; DATADDR = 0xff; //Se inicializan las interrupciones EICRA= 0xFF; EICRB= 0xFF; /**Se habilitan las interrupciones */ sei(); //*puntresetPushed=&variablesJuego.resetPushed; //Se inicializan las variables necesarias para jugar ReiniciarJuego(&variablesJuego); //Inicializar GLCD glcd_on(); glcd_clear(); loadingBar(); while(1) { sei(); //Se habilita que solo se puedan usar los botones de arriba, abajo y seleccionar EIMSK= 0x07; //Despliega el menu de seleccion de los niveles menu(&variablesJuego.posCursor,&variablesJuego.seleccionScreen); //Se habilita que se puedan usar todos los botones EIMSK= 0xFF; rellenarCasillas(variablesJuego.tablero1,variablesJuego.posCursor,&variablesJuego); variablesJuego.inGame=True; DrawScore(); while (endGame(variablesJuego.tablero1)==1 && variablesJuego.puntuacion>0 && variablesJuego.resetPushed==False) { glcd_putchar(42,variablesJuego.cursorPantalla.y,variablesJuego.cursorPantalla.x,0,2); _delay_ms(500); glcd_putchar(variablesJuego.valorCasilla,variablesJuego.cursorPantalla.y,variablesJuego.cursorPantalla.x,0,2); _delay_ms(500); } cli (); if (variablesJuego.puntuacion==0 && endGame(variablesJuego.tablero1)==1) { glcd_clear(); _delay_ms(500); glcd_puts("You Have Lost",5,3,0,1,0); _delay_ms(500); glcd_puts("Puntuacion 0",5,5,0,1,0); _delay_ms(500); } if (endGame(variablesJuego.tablero1)==0 ||(endGame(variablesJuego.tablero1)==0 && variablesJuego.puntuacion==0)) { glcd_clear(); _delay_ms(500); glcd_puts("You have Won",5,3,0,1,0); _delay_ms(500); glcd_puts("Puntuacion",5,5,0,1,0); _delay_ms(500); glcd_puts(itoa (variablesJuego.puntuacion,variablesJuego.puntuacion_pantalla,10),25,6,0,1,0); _delay_ms(700); } if(variablesJuego.resetPushed==True) { glcd_clear(); _delay_ms(500); glcd_puts("You have Won",5,3,0,1,0); _delay_ms(500); glcd_puts("Puntuacion",5,5,0,1,0); _delay_ms(500); glcd_puts(itoa (variablesJuego.puntuacion,variablesJuego.puntuacion_pantalla,10),25,6,0,1,0); _delay_ms(1000); } //Se reinicializan las variables ReiniciarJuego(&variablesJuego); //TODO:: Please write your application code } }