void mainboard_romstage_entry(struct romstage_params *rp)
{
struct pei_data pei_data;
post_code(0x31);
if (rp->power_state->prev_sleep_state != SLEEP_STATE_S3)
google_chromeec_kbbacklight(100);
printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version());
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);
/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&pei_data);
rp->pei_data = &pei_data;
/* Initalize memory */
romstage_common(rp);
/* Bring SSD out of reset */
set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH);
/*
* Enable PP3300_AUTOBAHN_EN after initial GPIO setup
* to prevent possible brownout.
*/
set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH);
}
void bootblock_mainboard_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
early_config_gpio();
}
void mainboard_romstage_entry(struct romstage_params *params)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
early_config_gpio();
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
romstage_common(params);
}
void mainboard_romstage_entry(struct romstage_params *params)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
/* Turn on keyboard backlight to indicate we are booting */
if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
google_chromeec_kbbacklight(100);
early_config_gpio();
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
romstage_common(params);
}
/* Entry from cache-as-ram.inc. */
void * asmlinkage romstage_main(unsigned long bist,
uint32_t tsc_low, uint32_t tsc_hi)
{
struct romstage_params rp = {
.bist = bist,
.mrc_params = NULL,
};
/* Save initial timestamp from bootblock. */
timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
program_base_addresses();
tco_disable();
byt_config_com1_and_enable();
console_init();
spi_init();
set_max_freq();
punit_init();
gfx_init();
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
return setup_stack_and_mttrs();
}
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
{
/* Initialize timestamp book keeping only once. */
timestamp_init(car_params->tsc);
/* Call into pre-console init code then initialize console. */
car_soc_pre_console_init();
car_mainboard_pre_console_init();
console_init();
printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE ||
car_params->bootloader_car_end !=
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)) {
printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
CONFIG_DCACHE_RAM_BASE,
CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
(long)car_params->bootloader_car_start,
(long)car_params->bootloader_car_end);
}
car_soc_post_console_init();
car_mainboard_post_console_init();
/* Ensure the EC is in the right mode for recovery */
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
!IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
google_chromeec_early_init();
set_fih_car(car_params->fih);
/* Return new stack value in ram back to assembly stub. */
return cache_as_ram_stage_main(car_params->fih);
}
void mainboard_romstage_entry(struct romstage_params *params)
{
/* PCH_MEM_CFG[3:0] */
gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
early_config_gpio();
params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
ARRAY_SIZE(spd_gpios));
/* Fill out PEI DATA */
mainboard_fill_pei_data(params->pei_data);
mainboard_fill_spd_data(params->pei_data);
/* Initliaze memory */
romstage_common(params);
}
void mainboard_romstage_entry(struct romstage_params *rp)
{
struct pei_data pei_data;
post_code(0x32);
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);
/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&pei_data);
rp->pei_data = &pei_data;
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
/* Do variant-specific (read: Samus) init */
variant_romstage_entry(rp);
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
struct romstage_handoff *handoff;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time =
(uint64_t)pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 32 ||
pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
start_romstage_time = timestamp_get();
#endif
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = wake_from_s3;
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
post_code(0x3f);
#if CONFIG_CHROMEOS
init_chromeos(boot_mode);
#endif
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
timestamp_add_now(TS_END_ROMSTAGE);
#endif
}
void romstage_common(const struct romstage_params *params)
{
int boot_mode;
int wake_from_s3;
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (params->bist == 0)
enable_lapic();
wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config);
#if CONFIG_EC_GOOGLE_CHROMEEC
/* Ensure the EC is in the right mode for recovery */
google_chromeec_early_init();
#endif
/* Halt if there was a built in self test failure */
report_bist_failure(params->bist);
/* Perform some early chipset initialization required
* before RAM initialization can work
*/
haswell_early_initialization(HASWELL_MOBILE);
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
#if CONFIG_HAVE_ACPI_RESUME
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
wake_from_s3 = 0;
#endif
}
/* There are hard coded assumptions of 2 meaning s3 wake. Normalize
* the users of the 2 literal here based off wake_from_s3. */
boot_mode = wake_from_s3 ? 2 : 0;
/* Prepare USB controller early in S3 resume */
if (wake_from_s3)
enable_usb_bar();
post_code(0x3a);
params->pei_data->boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM);
report_platform_info();
if (params->copy_spd != NULL)
params->copy_spd(params->pei_data);
sdram_initialize(params->pei_data);
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x3b);
intel_early_me_status();
quick_ram_check();
post_code(0x3e);
if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
/* Failed S3 resume, reset to come up cleanly */
reset_system();
#endif
}
romstage_handoff_init(wake_from_s3);
post_code(0x3f);
if (IS_ENABLED(CONFIG_LPC_TPM))
init_tpm(wake_from_s3);
}
static void vboot_prepare(void)
{
if (verification_should_run()) {
/* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */
verstage_main();
car_set_var(vboot_executed, 1);
vb2_save_recovery_reason_vbnv();
/*
* Avoid double memory retrain when the EC is running RW code
* and a recovery request came in through an EC host event. The
* double retrain happens because the EC won't be rebooted
* until kernel verification notices the EC isn't running RO
* code which is after memory training. Therefore, reboot the
* EC after we've saved the potential recovery request so it's
* not lost. Lastly, only perform this sequence on x86
* platforms since those are the ones that currently do a
* costly memory training in recovery mode.
*/
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
IS_ENABLED(CONFIG_ARCH_X86))
google_chromeec_early_init();
} else if (verstage_should_load()) {
struct cbfsf file;
struct prog verstage =
PROG_INIT(PROG_VERSTAGE,
CONFIG_CBFS_PREFIX "/verstage");
printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n");
/* load verstage from RO */
if (cbfs_boot_locate(&file, prog_name(&verstage), NULL))
die("failed to load verstage");
cbfs_file_data(prog_rdev(&verstage), &file);
if (cbfs_prog_stage_load(&verstage))
die("failed to load verstage");
/* verify and select a slot */
prog_run(&verstage);
/* This is not actually possible to hit this condition at
* runtime, but this provides a hint to the compiler for dead
* code elimination below. */
if (!IS_ENABLED(CONFIG_VBOOT_RETURN_FROM_VERSTAGE))
return;
car_set_var(vboot_executed, 1);
}
/*
* Fill in vboot cbmem objects before moving to ramstage so all
* downstream users have access to vboot results. This path only
* applies to platforms employing VBOOT_STARTS_IN_ROMSTAGE because
* cbmem comes online prior to vboot verification taking place. For
* other platforms the vboot cbmem objects are initialized when
* cbmem comes online.
*/
if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)) {
vb2_store_selected_region();
vboot_fill_handoff();
}
}
