/* We assume only one SPI port in the chip, one SPI device */
int spi_enable(int port, int enable)
{
if (enable) {
/*
* bit[5:4]
* 00b: SPI channel 0 and channel 1 are disabled.
* 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled.
* 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled.
* 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled.
*/
if (port == SSPI_CH_CS1)
IT83XX_GPIO_GRC1 |= 0x20;
else
IT83XX_GPIO_GRC1 |= 0x10;
gpio_config_module(MODULE_SPI, 1);
} else {
if (port == SSPI_CH_CS1)
IT83XX_GPIO_GRC1 &= ~0x20;
else
IT83XX_GPIO_GRC1 &= ~0x10;
gpio_config_module(MODULE_SPI, 0);
}
return EC_SUCCESS;
}
/**
* PWM configuration.
*
* @param ch operation channel
* @return none
*/
void pwm_config(enum pwm_channel ch)
{
pwm_init_ch = ch;
/* Configure pins from GPIOs to PWM */
if (ch == PWM_CH_FAN)
gpio_config_module(MODULE_PWM_FAN, 1);
else
gpio_config_module(MODULE_PWM_KBLIGHT, 1);
/* Disable PWM for module configuration */
pwm_enable(ch, 0);
/* Set PWM heartbeat mode is no heartbeat*/
NPCX_PWMCTL(pwm_channels[ch].channel) =
(NPCX_PWMCTL(pwm_channels[ch].channel)
&(~(((1<<2)-1)<<NPCX_PWMCTL_HB_DC_CTL)))
|(NPCX_PWM_HBM_NORMAL<<NPCX_PWMCTL_HB_DC_CTL);
/* Set PWM operation frequence */
pwm_freq_changed();
/* Set PWM cycle time */
NPCX_CTR(pwm_channels[ch].channel) =
(pwm_channels[ch].cycle_pulses - 1);
/* Set the duty cycle */
NPCX_DCR(pwm_channels[ch].channel) = 0;
/* Set PWM polarity is normal*/
CLEAR_BIT(NPCX_PWMCTL(pwm_channels[ch].channel), NPCX_PWMCTL_INVP);
/* Set PWM open drain output is push-pull type*/
CLEAR_BIT(NPCX_PWMCTL(pwm_channels[ch].channel), NPCX_PWMCTLEX_OD_OUT);
/* Select default CLK or LFCLK clock input to PWM module */
NPCX_PWMCTLEX(pwm_channels[ch].channel) =
(NPCX_PWMCTLEX(pwm_channels[ch].channel)
& (~(((1<<2)-1)<<NPCX_PWMCTLEX_FCK_SEL)))
| (NPCX_PWM_CLOCK_APB2_LFCLK<<NPCX_PWMCTLEX_FCK_SEL);
if (ch == PWM_CH_FAN) {
#ifdef CONFIG_PWM_INPUT_LFCLK
/* Select default LFCLK clock input to PWM module */
SET_BIT(NPCX_PWMCTL(pwm_channels[ch].channel),
NPCX_PWMCTL_CKSEL);
#else
/* Select default core clock input to PWM module */
CLEAR_BIT(NPCX_PWMCTL(pwm_channels[ch].channel),
NPCX_PWMCTL_CKSEL);
#endif
} else {
/* Select default core clock input to PWM module */
CLEAR_BIT(NPCX_PWMCTL(pwm_channels[ch].channel),
NPCX_PWMCTL_CKSEL);
}
}
void usb_spi_task(void)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
gpio_config_module(MODULE_SPI_MASTER, 1);
/* Set all four SPI pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
spi_enable(1);
while (1) {
task_wait_event(-1);
while (usb_spi_service_request(&usb_spi))
;
}
}
void board_config_post_gpio_init(void)
{
/* We use MCO2 clock passthrough to provide a clock to USB HS */
gpio_config_module(MODULE_MCO, 1);
/* GPIO PC9 to high speed */
GPIO_SET_HS(C, 9);
if (usb_ctl.phy_type == USB_PHY_ULPI)
gpio_set_level(GPIO_USB_MUX_SEL, 0);
else
gpio_set_level(GPIO_USB_MUX_SEL, 1);
/* Set USB GPIO to high speed */
GPIO_SET_HS(A, 11);
GPIO_SET_HS(A, 12);
GPIO_SET_HS(C, 3);
GPIO_SET_HS(C, 2);
GPIO_SET_HS(C, 0);
GPIO_SET_HS(A, 5);
GPIO_SET_HS(B, 5);
GPIO_SET_HS(B, 13);
GPIO_SET_HS(B, 12);
GPIO_SET_HS(B, 2);
GPIO_SET_HS(B, 10);
GPIO_SET_HS(B, 1);
GPIO_SET_HS(B, 0);
GPIO_SET_HS(A, 3);
}
void board_config_post_gpio_init(void)
{
/* We use MCO2 clock passthrough to provide a clock to USB HS */
gpio_config_module(MODULE_MCO, 1);
/* GPIO PC9 to high speed */
GPIO_SET_HS(C, 9);
/* Set USB GPIO to high speed */
GPIO_SET_HS(A, 11);
GPIO_SET_HS(A, 12);
GPIO_SET_HS(C, 3);
GPIO_SET_HS(C, 2);
GPIO_SET_HS(C, 0);
GPIO_SET_HS(A, 5);
GPIO_SET_HS(B, 5);
GPIO_SET_HS(B, 13);
GPIO_SET_HS(B, 12);
GPIO_SET_HS(B, 2);
GPIO_SET_HS(B, 10);
GPIO_SET_HS(B, 1);
GPIO_SET_HS(B, 0);
GPIO_SET_HS(A, 3);
/* Set I2C GPIO to HS */
GPIO_SET_HS(B, 6);
GPIO_SET_HS(B, 7);
GPIO_SET_HS(F, 1);
GPIO_SET_HS(F, 0);
GPIO_SET_HS(A, 8);
GPIO_SET_HS(B, 4);
GPIO_SET_HS(C, 6);
GPIO_SET_HS(C, 7);
}
/**
* Enable and disable SPI for case closed debugging. This forces the AP into
* reset while SPI is enabled, thus preventing contention on the SPI interface.
*/
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Place AP into reset */
gpio_set_level(GPIO_PMIC_WARM_RESET_L, 0);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);
gpio_set_flags(SPI_FLASH_DEVICE->gpio_cs, GPIO_OUT_HIGH);
/* Set all four SPI pins to high speed */
/* pins B10/B14/B15 and B9 */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xf03c0000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
/* Enable SPI LDO to power the flash chip */
gpio_set_level(GPIO_VDDSPI_EN, 1);
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
void board_hibernate_late(void)
{
int i;
const uint32_t hibernate_pins[][2] = {
/* Turn off LEDs in hibernate */
{GPIO_BAT_LED_BLUE, GPIO_INPUT | GPIO_PULL_UP},
{GPIO_BAT_LED_AMBER, GPIO_INPUT | GPIO_PULL_UP},
{GPIO_LID_OPEN, GPIO_INT_RISING | GPIO_PULL_DOWN},
/*
* BD99956 handles charge input automatically. We'll disable
* charge output in hibernate. Charger will assert ACOK_OD
* when VBUS or VCC are plugged in.
*/
{GPIO_USB_C0_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN},
{GPIO_USB_C1_5V_EN, GPIO_INPUT | GPIO_PULL_DOWN},
};
/* Change GPIOs' state in hibernate for better power consumption */
for (i = 0; i < ARRAY_SIZE(hibernate_pins); ++i)
gpio_set_flags(hibernate_pins[i][0], hibernate_pins[i][1]);
gpio_config_module(MODULE_KEYBOARD_SCAN, 0);
/*
* Calling gpio_config_module sets disabled alternate function pins to
* GPIO_INPUT. But to prevent keypresses causing leakage currents
* while hibernating we want to enable GPIO_PULL_UP as well.
*/
gpio_set_flags_by_mask(0x2, 0x03, GPIO_INPUT | GPIO_PULL_UP);
gpio_set_flags_by_mask(0x1, 0xFF, GPIO_INPUT | GPIO_PULL_UP);
gpio_set_flags_by_mask(0x0, 0xE0, GPIO_INPUT | GPIO_PULL_UP);
}
void uart_init(void)
{
long long setting = (16 * (1 << UART_NCO_WIDTH) *
(long long)CONFIG_UART_BAUD_RATE / PCLK_FREQ);
/* turn on uart clock */
clock_enable_module(MODULE_UART, 1);
/* set up pinmux */
gpio_config_module(MODULE_UART, 1);
/* set frequency */
GR_UART_NCO(0) = setting;
/* Interrupt when RX fifo has anything, when TX fifo <= half empty */
/* Also reset (clear) both FIFOs */
GR_UART_FIFO(0) = 0x63;
/* TX enable, RX enable, HW flow control disabled, no loopback */
GR_UART_CTRL(0) = 0x03;
/* enable RX interrupts in block */
/* Note: doesn't do anything unless turned on in NVIC */
GR_UART_ICTRL(0) = 0x02;
/* Enable interrupts for UART0 only */
uart_enable_interrupt();
done_uart_init_yet = 1;
}
static void i2c_init(void)
{
int i;
/* Configure GPIOs */
gpio_config_module(MODULE_I2C, 1);
for (i = 0; i < i2c_ports_used; ++i)
configure_port(i2c_ports[i].port, i2c_ports[i].kbps);
}
void keyboard_raw_init(void)
{
keyboard_raw_enable_interrupt(0);
gpio_config_module(MODULE_KEYBOARD_SCAN, 1);
/* Enable keyboard scan interrupt */
MEC1322_INT_ENABLE(17) |= 1 << 21;
MEC1322_INT_BLK_EN |= 1 << 17;
MEC1322_KS_KSI_INT_EN = 0xff;
}
void usb_spi_board_disable(struct usb_spi_config const *config)
{
spi_enable(CONFIG_SPI_FLASH_PORT, 0);
/* Disable clocks to SPI2 module */
STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
/* Release SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 0);
}
static void spi_chipset_shutdown(void)
{
enabled = 0;
state = SPI_STATE_DISABLED;
/* Disable pullup and interrupts on NSS */
gpio_set_flags(GPIO_SPI1_NSS, GPIO_INPUT);
/* Set SPI pins to inputs so we don't leak power when AP is off */
gpio_config_module(MODULE_SPI, 0);
}
/**
* Set SPI enabled.
*
* @spi_port port to act on. Only one port supported, one gpio.
* @param enable enabled flag
* @return success
*/
int spi_enable(int port, int enable)
{
int i;
enum gpio_signal gpio;
if (enable) {
/* Enabling spi module for gpio configuration */
gpio_config_module(MODULE_SPI, 1);
/* GPIO No SPI Select */
CLEAR_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
for (i = 0; i < spi_devices_used; i++) {
if (spi_devices[i].port != port)
continue;
gpio = spi_devices[i].gpio_cs;
/* Make sure CS# is a GPIO output mode. */
gpio_set_flags(gpio, GPIO_OUTPUT);
/* Make sure CS# is deselected */
gpio_set_level(gpio, 1);
}
/* Enabling spi module */
SET_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
} else {
/* Disabling spi module */
CLEAR_BIT(NPCX_SPI_CTL1, NPCX_SPI_CTL1_SPIEN);
for (i = 0; i < spi_devices_used; i++) {
if (spi_devices[i].port != port)
continue;
gpio = spi_devices[i].gpio_cs;
/* Make sure CS# is deselected */
gpio_set_level(gpio, 1);
gpio_set_flags(gpio, GPIO_ODR_HIGH);
}
/* Disabling spi module for gpio configuration */
gpio_config_module(MODULE_SPI, 0);
/* GPIO No SPI Select */
SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP);
}
return EC_SUCCESS;
}
/**
* Initialize on the specified I2C port.
*
* @param p the I2c port
*/
static void i2c_init_port(const struct i2c_port_t *p)
{
int port = p->port;
enum stm32_i2c_clk_src src = I2C_CLK_SRC_48MHZ;
enum i2c_freq freq;
/* Enable clocks to I2C modules if necessary */
if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
STM32_RCC_APB1ENR |= 1 << (21 + port);
if (port == STM32_I2C1_PORT) {
#if defined(CONFIG_HOSTCMD_I2C_SLAVE_ADDR) && \
defined(CONFIG_LOW_POWER_IDLE) && \
(I2C_PORT_EC == STM32_I2C1_PORT)
/*
* Use HSI (8MHz) for i2c clock. This allows smooth wakeup
* from STOP mode since HSI is only clock running immediately
* upon exit from STOP mode.
*/
STM32_RCC_CFGR3 &= ~0x10;
src = I2C_CLK_SRC_8MHZ;
#else
/* Use SYSCLK for i2c clock. */
STM32_RCC_CFGR3 |= 0x10;
#endif
}
/* Configure GPIOs */
gpio_config_module(MODULE_I2C, 1);
/* Set clock frequency */
switch (p->kbps) {
case 1000:
freq = I2C_FREQ_1000KHZ;
break;
case 400:
freq = I2C_FREQ_400KHZ;
break;
case 100:
freq = I2C_FREQ_100KHZ;
break;
default: /* unknown speed, defaults to 100kBps */
CPRINTS("I2C bad speed %d kBps", p->kbps);
freq = I2C_FREQ_100KHZ;
}
/* Set up initial bus frequencies */
i2c_set_freq_port(p, src, freq);
/* Set up default timeout */
i2c_set_timeout(port, 0);
}
static void led_init(void)
{
/* Configure GPIOs */
gpio_config_module(MODULE_PWM_LED, 1);
/*
* Enable PWMs and set to 0% duty cycle. If they're disabled, the LM4
* seems to ground the pins instead of letting them float.
*/
pwm_enable(PWM_CH_LED_RED, 1);
pwm_enable(PWM_CH_LED_GREEN, 1);
set_color(LED_OFF);
}
static void spi_chipset_startup(void)
{
/* Enable pullup and interrupts on NSS */
gpio_set_flags(GPIO_SPI1_NSS, GPIO_INT_BOTH | GPIO_PULL_UP);
/* Set SPI pins to alternate function */
gpio_config_module(MODULE_SPI, 1);
/* Set up for next transaction */
setup_for_transaction();
enabled = 1;
}
/**
* Initialize on the specified I2C port.
*
* @param p the I2c port
*/
static void i2c_init_port(const struct i2c_port_t *p)
{
int port = p->port;
/* Enable clocks to I2C modules if necessary */
if (!(STM32_RCC_APB1ENR & (1 << (21 + port))))
STM32_RCC_APB1ENR |= 1 << (21 + port);
/* Configure GPIOs */
gpio_config_module(MODULE_I2C, 1);
/* Set up initial bus frequencies */
i2c_set_freq_port(p);
}
void usb_spi_board_disable(struct usb_spi_config const *config)
{
spi_enable(CONFIG_SPI_FLASH_PORT, 0);
/* Disable SPI LDO */
gpio_set_level(GPIO_VDDSPI_EN, 0);
/* Disable clocks to SPI2 module */
STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
/* Release SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 0);
gpio_set_flags(SPI_FLASH_DEVICE->gpio_cs, GPIO_INPUT);
/* Release AP from reset */
gpio_set_level(GPIO_PMIC_WARM_RESET_L, 1);
}
static void peci_init(void)
{
int i;
/* Enable the PECI module in run and sleep modes. */
clock_enable_peripheral(CGC_OFFSET_PECI, 0x1,
CGC_MODE_RUN | CGC_MODE_SLEEP);
/* Configure GPIOs */
gpio_config_module(MODULE_PECI, 1);
/* Set initial clock frequency */
peci_freq_changed();
/* Initialize temperature reading buffer to a sane value. */
for (i = 0; i < TEMP_AVG_LENGTH; ++i)
temp_vals[i] = 300; /* 27 C */
}
static void pwm_kblight_init(void)
{
const struct pwm_kbd_state *prev;
int version, size;
/* Configure GPIO */
gpio_config_module(MODULE_PWM_KBLIGHT, 1);
prev = (const struct pwm_kbd_state *)
system_get_jump_tag(PWMKBD_SYSJUMP_TAG, &version, &size);
if (prev && version == PWM_HOOK_VERSION && size == sizeof(*prev)) {
/* Restore previous state. */
pwm_enable(PWM_CH_KBLIGHT, prev->kblight_en);
pwm_set_duty(PWM_CH_KBLIGHT, prev->kblight_percent);
} else {
/* Enable keyboard backlight control, turned down */
pwm_set_duty(PWM_CH_KBLIGHT, 0);
pwm_enable(PWM_CH_KBLIGHT, 1);
}
}
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);
/* Set all four SPI pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
void usb_spi_board_enable(struct usb_spi_config const *config)
{
/* Remap SPI2 to DMA channels 6 and 7 */
/* STM32F072 SPI2 defaults to using DMA channels 4 and 5 */
/* but cros_ec hardcodes a 6/7 assumption in registers.h */
STM32_SYSCFG_CFGR1 |= (1 << 24);
/* Configure SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 1);
/* Set all four SPI pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2;
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
/*
* Most registers in LPC module are reset when the host is off. We need to
* set up LPC again when the host is starting up.
*/
static void setup_lpc(void)
{
gpio_config_module(MODULE_LPC, 1);
/* Set up interrupt on LRESET# deassert */
MEC1322_INT_SOURCE(19) = 1 << 1;
MEC1322_INT_ENABLE(19) |= 1 << 1;
MEC1322_INT_BLK_EN |= 1 << 19;
task_enable_irq(MEC1322_IRQ_GIRQ19);
/* Set up ACPI0 for 0x62/0x66 */
MEC1322_LPC_ACPI_EC0_BAR = 0x00628304;
MEC1322_INT_ENABLE(15) |= 1 << 6;
MEC1322_INT_BLK_EN |= 1 << 15;
/* Clear STATUS_PROCESSING bit in case it was set during sysjump */
MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING;
task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF);
/* Set up ACPI1 for 0x200/0x204 */
MEC1322_LPC_ACPI_EC1_BAR = 0x02008407;
MEC1322_INT_ENABLE(15) |= 1 << 8;
MEC1322_INT_BLK_EN |= 1 << 15;
MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF);
/* Set up 8042 interface at 0x60/0x64 */
MEC1322_LPC_8042_BAR = 0x00608104;
/* Set up indication of Auxillary sts */
MEC1322_8042_KB_CTRL |= 1 << 7;
MEC1322_8042_ACT |= 1;
MEC1322_INT_ENABLE(15) |= ((1 << 13) | (1 << 14));
MEC1322_INT_BLK_EN |= 1 << 15;
task_enable_irq(MEC1322_IRQ_8042EM_IBF);
task_enable_irq(MEC1322_IRQ_8042EM_OBF);
#ifndef CONFIG_KEYBOARD_IRQ_GPIO
/* Set up SERIRQ for keyboard */
MEC1322_8042_KB_CTRL |= (1 << 5);
MEC1322_LPC_SIRQ(1) = 0x01;
#endif
/* Set up EMI module for memory mapped region, base address 0x800 */
MEC1322_LPC_EMI_BAR = 0x0800800f;
MEC1322_INT_ENABLE(15) |= 1 << 2;
MEC1322_INT_BLK_EN |= 1 << 15;
task_enable_irq(MEC1322_IRQ_EMI);
/* Access data RAM through alias address */
MEC1322_EMI_MBA0 = (uint32_t)mem_mapped - 0x118000 + 0x20000000;
/*
* Limit EMI read / write range. First 256 bytes are RW for host
* commands. Second 256 bytes are RO for mem-mapped data.
*/
MEC1322_EMI_MRL0 = 0x200;
MEC1322_EMI_MWL0 = 0x100;
/* Set up Mailbox for Port80 trapping */
MEC1322_MBX_INDEX = 0xff;
MEC1322_LPC_MAILBOX_BAR = 0x00808901;
/* We support LPC args and version 3 protocol */
*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
EC_HOST_CMD_FLAG_VERSION_3;
/* Sufficiently initialized */
init_done = 1;
/* Update host events now that we can copy them to memmap */
update_host_event_status();
}
/* init ADC ports to avoid floating state due to thermistors */
static void adc_pre_init(void)
{
/* Configure GPIOs */
gpio_config_module(MODULE_ADC, 1);
}
static void lpc_init(void)
{
/* Enable LPC clock in run and sleep modes. */
clock_enable_peripheral(CGC_OFFSET_LPC, 0x1,
CGC_MODE_RUN | CGC_MODE_SLEEP);
LM4_LPC_LPCIM = 0;
LM4_LPC_LPCCTL = 0;
LM4_LPC_LPCIRQCTL = 0;
/* Configure GPIOs */
gpio_config_module(MODULE_LPC, 1);
/*
* Set LPC channel 0 to I/O address 0x62 (data) / 0x66 (command),
* single endpoint, offset 0 for host command/writes and 1 for EC
* data writes, pool bytes 0(data)/1(cmd)
*/
LM4_LPC_ADR(LPC_CH_ACPI) = EC_LPC_ADDR_ACPI_DATA;
LM4_LPC_CTL(LPC_CH_ACPI) = (LPC_POOL_OFFS_ACPI << (5 - 1));
LM4_LPC_ST(LPC_CH_ACPI) = 0;
/* Unmask interrupt for host command and data writes */
LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_ACPI, 6);
/*
* Set LPC channel 1 to I/O address 0x80 (data), single endpoint,
* pool bytes 4(data)/5(cmd).
*/
LM4_LPC_ADR(LPC_CH_PORT80) = 0x80;
LM4_LPC_CTL(LPC_CH_PORT80) = (LPC_POOL_OFFS_PORT80 << (5 - 1));
/* Unmask interrupt for host data writes */
LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_PORT80, 2);
/*
* Set LPC channel 2 to I/O address 0x880, range endpoint,
* arbitration disabled, pool bytes 512-639. To access this from
* x86, use the following command to set GEN_LPC2:
*
* pci_write32 0 0x1f 0 0x88 0x007c0801
*/
LM4_LPC_ADR(LPC_CH_CMD_DATA) = EC_LPC_ADDR_HOST_ARGS;
LM4_LPC_CTL(LPC_CH_CMD_DATA) = 0x8019 |
(LPC_POOL_OFFS_CMD_DATA << (5 - 1));
/*
* Set LPC channel 3 to I/O address 0x60 (data) / 0x64 (command),
* single endpoint, offset 0 for host command/writes and 1 for EC
* data writes, pool bytes 0(data)/1(cmd)
*/
LM4_LPC_ADR(LPC_CH_KEYBOARD) = 0x60;
LM4_LPC_CTL(LPC_CH_KEYBOARD) = (1 << 24/* IRQSEL1 */) |
(0 << 18/* IRQEN1 */) | (LPC_POOL_OFFS_KEYBOARD << (5 - 1));
LM4_LPC_ST(LPC_CH_KEYBOARD) = 0;
/* Unmask interrupt for host command/data writes and data reads */
LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_KEYBOARD, 7);
/*
* Set LPC channel 4 to I/O address 0x200 (data) / 0x204 (command),
* single endpoint, offset 0 for host command/writes and 1 for EC
* data writes, pool bytes 0(data)/1(cmd)
*/
LM4_LPC_ADR(LPC_CH_CMD) = EC_LPC_ADDR_HOST_DATA;
LM4_LPC_CTL(LPC_CH_CMD) = (LPC_POOL_OFFS_CMD << (5 - 1));
/*
* Initialize status bits to 0. We never set the ACPI burst status bit,
* so this guarantees that at least one status bit will always be 0.
* This is used by comm_lpc.c to detect that the EC is present on the
* LPC bus. See crosbug.com/p/10963.
*/
LM4_LPC_ST(LPC_CH_CMD) = 0;
/* Unmask interrupt for host command writes */
LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_CMD, 4);
/*
* Set LPC channel 5 to I/O address 0x900, range endpoint,
* arbitration enabled, pool bytes 768-1023. To access this from
* x86, use the following command to set GEN_LPC3:
*
* pci_write32 0 0x1f 0 0x8c 0x007c0901
*/
LM4_LPC_ADR(LPC_CH_MEMMAP) = EC_LPC_ADDR_MEMMAP;
LM4_LPC_CTL(LPC_CH_MEMMAP) = 0x0019 | (LPC_POOL_OFFS_MEMMAP << (5 - 1));
#ifdef CONFIG_UART_HOST
/*
* Set LPC channel 7 to COM port I/O address. Note that channel 7
* ignores the TYPE bit and is always an 8-byte range.
*/
LM4_LPC_ADR(LPC_CH_COMX) = LPC_COMX_ADDR;
/*
* In theory we could configure IRQSELs and set IRQEN2/CX, and then the
* host could enable IRQs on its own. So far that hasn't been
* necessary, and due to the issues with IRQs (see wait_irq_sent()
* above) it might not work anyway.
*/
LM4_LPC_CTL(LPC_CH_COMX) = 0x0004 | (LPC_POOL_OFFS_COMX << (5 - 1));
/* Enable COMx emulation for reads and writes. */
LM4_LPC_LPCDMACX = 0x00310000;
/*
* Unmask interrupt for host data writes. We don't need interrupts for
* reads, because there's no flow control in that direction; LPC is
* much faster than the UART, and the UART doesn't have anywhere
* sensible to buffer input anyway.
*/
LM4_LPC_LPCIM |= LM4_LPC_INT_MASK(LPC_CH_COMX, 2);
#endif /* CONFIG_UART_HOST */
/*
* Unmaksk LPC bus reset interrupt. This lets us monitor the PCH
* PLTRST# signal for debugging.
*/
LM4_LPC_LPCIM |= (1 << 31);
/* Enable LPC channels */
LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 |
(1 << LPC_CH_ACPI) |
(1 << LPC_CH_PORT80) |
(1 << LPC_CH_CMD_DATA) |
(1 << LPC_CH_KEYBOARD) |
(1 << LPC_CH_CMD) |
(1 << LPC_CH_MEMMAP);
#ifdef CONFIG_UART_HOST
LM4_LPC_LPCCTL |= 1 << LPC_CH_COMX;
#endif
/*
* Ensure the EC (slave) has control of the memory-mapped I/O space.
* Once the EC has won arbtration for the memory-mapped space, it will
* keep control of it until it writes the last byte in the space.
* (That never happens; we can't use the last byte in the space because
* ACPI can't see it anyway.)
*/
while (!(LM4_LPC_ST(LPC_CH_MEMMAP) & 0x10)) {
/* Clear HW1ST */
LM4_LPC_ST(LPC_CH_MEMMAP) &= ~0x40;
/* Do a dummy slave write; this should cause SW1ST to be set */
*LPC_POOL_MEMMAP = *LPC_POOL_MEMMAP;
}
/* Initialize host args and memory map to all zero */
memset(lpc_host_args, 0, sizeof(*lpc_host_args));
memset(lpc_get_memmap_range(), 0, EC_MEMMAP_SIZE);
/* We support LPC args and version 3 protocol */
*(lpc_get_memmap_range() + EC_MEMMAP_HOST_CMD_FLAGS) =
EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED |
EC_HOST_CMD_FLAG_VERSION_3;
/* Enable LPC interrupt */
task_enable_irq(LM4_IRQ_LPC);
#ifdef CONFIG_UART_HOST
/* Enable COMx UART */
uart_comx_enable();
#endif
/* Restore event masks if needed */
lpc_post_sysjump();
/* Sufficiently initialized */
init_done = 1;
/* Update host events now that we can copy them to memmap */
update_host_event_status();
}
static void i2c_init(void)
{
int i;
/* Configure pins from GPIOs to I2Cs */
gpio_config_module(MODULE_I2C, 1);
/* Enable clock for I2C peripheral */
clock_enable_peripheral(CGC_OFFSET_I2C, CGC_I2C_MASK,
CGC_MODE_RUN | CGC_MODE_SLEEP);
/* Set I2C freq */
i2c_freq_changed();
/*
* initialize smb status and register
*/
for (i = 0; i < i2c_ports_used; i++) {
int port = i2c_ports[i].port;
int ctrl = i2c_port_to_controller(port);
volatile struct i2c_status *p_status = i2c_stsobjs + ctrl;
/* Configure pull-up for SMB interface pins */
/* Enable 3.3V pull-up or turn to 1.8V support */
if (port == NPCX_I2C_PORT0_0) {
#ifdef NPCX_I2C0_0_1P8V
SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SC0_0_LV);
SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SD0_0_LV);
#else
SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0));
#endif
} else if (port == NPCX_I2C_PORT0_1) {
#ifdef NPCX_I2C0_1_1P8V
SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL0_SC0_1_LV);
SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL0_SD0_1_LV);
#else
SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 1));
#endif
} else if (port == NPCX_I2C_PORT1) {
#ifdef NPCX_I2C1_1P8V
SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SC1_0_LV);
SET_BIT(NPCX_LV_GPIO_CTL0, NPCX_LV_GPIO_CTL0_SD1_0_LV);
#else
SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0));
#endif
} else if (port == NPCX_I2C_PORT2) {
#ifdef NPCX_I2C2_1P8V
SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SC2_0_LV);
SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SD2_0_LV);
#else
SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0));
#endif
} else if (port == NPCX_I2C_PORT3) {
#ifdef NPCX_I2C3_1P8V
SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SC3_0_LV);
SET_BIT(NPCX_LV_GPIO_CTL1, NPCX_LV_GPIO_CTL1_SD3_0_LV);
#else
SET_BIT(NPCX_DEVPU0, NPCX_I2C_PUBIT(ctrl, 0));
#endif
}
/* Enable module - before configuring CTL1 */
SET_BIT(NPCX_SMBCTL2(ctrl), NPCX_SMBCTL2_ENABLE);
/* status init */
p_status->oper_state = SMB_IDLE;
/* Reset task ID */
p_status->task_waiting = TASK_ID_INVALID;
/* Enable event and error interrupts */
task_enable_irq(i2c_irqs[ctrl]);
/* Use default timeout. */
i2c_set_timeout(port, 0);
}
}
/* Initialize all PWM pins as functional */
static void pwm_pin_init(void)
{
gpio_config_module(MODULE_PWM, 1);
}
static void i2c_init(void)
{
int i, p, p_ch;
/* Configure GPIOs */
gpio_config_module(MODULE_I2C, 1);
#ifdef CONFIG_IT83XX_SMCLK2_ON_GPC7
/* bit7, 0: SMCLK2 is located on GPF6, 1: SMCLK2 is located on GPC7 */
IT83XX_GPIO_GRC7 |= 0x80;
#endif
/* Enable I2C function. */
for (i = 0; i < i2c_ports_used; i++) {
/* I2c port mapping. */
p = i2c_ports[i].port;
clock_enable_peripheral(i2c_ctrl_regs[p].clock_gate, 0, 0);
if (p < I2C_STANDARD_PORT_COUNT) {
/*
* bit0, The SMBus host interface is enabled.
* bit1, Enable to communicate with I2C device
* and support I2C-compatible cycles.
* bit4, This bit controls the reset mechanism
* of SMBus master to handle the SMDAT
* line low if 25ms reg timeout.
*/
IT83XX_SMB_HOCTL2(p) = 0x11;
/*
* bit1, Kill SMBus host transaction.
* bit0, Enable the interrupt for the master interface.
*/
IT83XX_SMB_HOCTL(p) = 0x03;
IT83XX_SMB_HOCTL(p) = 0x01;
/* W/C host status register */
IT83XX_SMB_HOSTA(p) = HOSTA_ALL_WC_BIT;
IT83XX_SMB_HOCTL2(p) = 0x00;
} else {
/* Shift register */
p_ch = i2c_ch_reg_shift(p);
switch (p) {
case IT83XX_I2C_CH_D:
#ifndef CONFIG_UART_HOST
/* Enable SMBus D channel */
IT83XX_GPIO_GRC2 |= 0x20;
#endif
break;
case IT83XX_I2C_CH_E:
/* Enable SMBus E channel */
IT83XX_GCTRL_PMER1 |= 0x01;
break;
case IT83XX_I2C_CH_F:
/* Enable SMBus F channel */
IT83XX_GCTRL_PMER1 |= 0x02;
break;
}
/* Software reset */
IT83XX_I2C_DHTR(p_ch) |= 0x80;
IT83XX_I2C_DHTR(p_ch) &= 0x7F;
/* State reset and hardware reset */
IT83XX_I2C_CTR(p_ch) = 0x11;
IT83XX_I2C_CTR(p_ch) = 0x00;
/* Set time out condition */
IT83XX_I2C_TOR(p_ch) = 0xFF;
IT83XX_I2C_T_BUF(p_ch) = 0x3F;
/*
* bit3, Acknowledge
* bit5, Master mode
* bit6, Interrupt enable
*/
IT83XX_I2C_CTR(p_ch) = 0x68;
/*
* bit1, Module enable
* bit4-6 Support number of devices
*/
IT83XX_I2C_CTR1(p_ch) = 0x00;
}
pdata[i].task_waiting = TASK_ID_INVALID;
}
i2c_freq_changed();
for (i = 0; i < I2C_PORT_COUNT; i++) {
/* Use default timeout */
i2c_set_timeout(i, 0);
}
}
void usb_init(void)
{
int i, resume;
/* USB is in use */
disable_sleep(SLEEP_MASK_USB_DEVICE);
/*
* Resuming from a deep sleep is a lot like a cold boot, but there are
* few things that we need to do slightly differently. However, we ONLY
* do them if we're really resuming due to a USB wakeup. If we're woken
* for some other reason, we just do a normal USB reset. The host
* doesn't mind.
*/
resume = ((system_get_reset_flags() & RESET_FLAG_USB_RESUME) &&
(GR_USB_GINTSTS & GC_USB_GINTSTS_WKUPINT_MASK));
/* TODO(crosbug.com/p/46813): Clean this up. Do only what's needed, and
* use meaningful constants instead of magic numbers. */
GREG32(GLOBALSEC, DDMA0_REGION0_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DDMA0_REGION1_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DDMA0_REGION2_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DDMA0_REGION3_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DUSB0_REGION0_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DUSB0_REGION1_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DUSB0_REGION2_CTRL) = 0xffffffff;
GREG32(GLOBALSEC, DUSB0_REGION3_CTRL) = 0xffffffff;
/* Enable clocks */
clock_enable_module(MODULE_USB, 1);
/* TODO(crbug.com/496888): set up pinmux */
gpio_config_module(MODULE_USB, 1);
/* Make sure interrupts are disabled */
GR_USB_GINTMSK = 0;
GR_USB_DAINTMSK = 0;
GR_USB_DIEPMSK = 0;
GR_USB_DOEPMSK = 0;
/* Select the correct PHY */
usb_select_phy(which_phy);
/* Full-Speed Serial PHY */
GR_USB_GUSBCFG = GUSBCFG_PHYSEL_FS | GUSBCFG_FSINTF_6PIN
| GUSBCFG_TOUTCAL(7)
/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
| GUSBCFG_USBTRDTIM(14);
if (!resume)
/* Don't reset on resume, because some preserved internal state
* will be lost and there's no way to restore it. */
usb_softreset();
GR_USB_GUSBCFG = GUSBCFG_PHYSEL_FS | GUSBCFG_FSINTF_6PIN
| GUSBCFG_TOUTCAL(7)
/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
| GUSBCFG_USBTRDTIM(14);
/* Global + DMA configuration */
/* TODO: What about the AHB Burst Length Field? It's 0 now. */
GR_USB_GAHBCFG = GAHBCFG_DMA_EN | GAHBCFG_GLB_INTR_EN |
GAHBCFG_NP_TXF_EMP_LVL;
/* Be in disconnected state until we are ready */
if (!resume)
usb_disconnect();
if (resume)
/* DEVADDR is preserved in the USB module during deep sleep,
* but it doesn't show up in USB_DCFG on resume. If we don't
* restore it manually too, it doesn't work. */
GR_USB_DCFG = GREG32(PMU, PWRDN_SCRATCH18);
else
/* Init: USB2 FS, Scatter/Gather DMA, DEVADDR = 0x00 */
GR_USB_DCFG |= DCFG_DEVSPD_FS48 | DCFG_DESCDMA;
/* If we've restored a nonzero device address, update our state. */
if (GR_USB_DCFG & GC_USB_DCFG_DEVADDR_MASK) {
/* Caution: We only have one config TODAY, so there's no real
* difference between DS_CONFIGURED and DS_ADDRESS. */
device_state = DS_CONFIGURED;
configuration_value = 1;
} else {
device_state = DS_DEFAULT;
configuration_value = 0;
}
/* Now that DCFG.DesDMA is accurate, prepare the FIFOs */
setup_data_fifos();
/* If resuming, reinitialize the endpoints now. For a cold boot we'll
* do this as part of handling the host-driven reset. */
if (resume)
usb_init_endpoints();
/* Clear any pending interrupts */
for (i = 0; i < 16; i++) {
GR_USB_DIEPINT(i) = 0xffffffff;
GR_USB_DOEPINT(i) = 0xffffffff;
}
GR_USB_GINTSTS = 0xFFFFFFFF;
/* Unmask some endpoint interrupt causes */
GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK;
GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK |
DOEPMSK_SETUPMSK;
/* Enable interrupt handlers */
task_enable_irq(GC_IRQNUM_USB0_USBINTR);
/* Allow USB interrupts to come in */
GR_USB_GINTMSK =
/* NAK bits that must be cleared by the DCTL register */
GINTMSK(GOUTNAKEFF) | GINTMSK(GINNAKEFF) |
/* Initialization events */
GINTMSK(USBRST) | GINTMSK(ENUMDONE) |
/* Endpoint activity, cleared by the DOEPINT/DIEPINT regs */
GINTMSK(OEPINT) | GINTMSK(IEPINT) |
/* Reset detected while suspended. Need to wake up. */
GINTMSK(RESETDET) | /* TODO: Do we need this? */
/* Idle, Suspend detected. Should go to sleep. */
GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP) |
/* Watch for first SOF */
GINTMSK(SOF);
/* Device registers have been setup */
GR_USB_DCTL |= DCTL_PWRONPRGDONE;
udelay(10);
GR_USB_DCTL &= ~DCTL_PWRONPRGDONE;
/* Clear global NAKs */
GR_USB_DCTL |= DCTL_CGOUTNAK | DCTL_CGNPINNAK;
#ifndef CONFIG_USB_INHIBIT_CONNECT
/* Indicate our presence to the USB host */
if (!resume)
usb_connect();
#endif
}
/* Initialize board. */
static void board_init(void)
{
int i;
/* Enable pericom BC1.2 interrupts. */
gpio_enable_interrupt(GPIO_USBC_BC12_INT_L);
/*
* Initialize AP console forwarding USART and queues.
*/
queue_init(&ap_usart_to_usb);
queue_init(&ap_usb_to_usart);
usart_init(&ap_usart);
/* Disable UART input when the Write Protect is enabled */
if (system_is_locked())
ap_usb.state->rx_disabled = 1;
/*
* Enable CC lines after all GPIO have been initialized. Note, it is
* important that this is enabled after the CC_DEVICE_ODL lines are
* set low to specify device mode.
*/
gpio_set_level(GPIO_USBC_CC_EN, 1);
/* Enable interrupts on VBUS transitions. */
gpio_enable_interrupt(GPIO_CHGR_ACOK);
/* Enable interrupts from BMI160 sensor. */
gpio_enable_interrupt(GPIO_ACC_IRQ1);
/* Enable interrupts from SI1141 sensor. */
gpio_enable_interrupt(GPIO_ALS_PROXY_INT_L);
if (board_has_spi_sensors()) {
for (i = MOTIONSENSE_TYPE_ACCEL;
i <= MOTIONSENSE_TYPE_MAG; i++) {
motion_sensors[i].addr =
BMI160_SET_SPI_ADDRESS(CONFIG_SPI_ACCEL_PORT);
}
/* SPI sensors: put back the GPIO in its expected state */
gpio_set_level(GPIO_SPI3_NSS, 1);
/* Enable SPI for BMI160 */
gpio_config_module(MODULE_SPI_MASTER, 1);
/* Set all four SPI3 pins to high speed */
/* pins C10/C11/C12 */
STM32_GPIO_OSPEEDR(GPIO_C) |= 0x03f00000;
/* pin A4 */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0x00000300;
/* Enable clocks to SPI3 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI3;
/* Reset SPI3 */
STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI3;
STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI3;
spi_enable(CONFIG_SPI_ACCEL_PORT, 1);
CPRINTS("Board using SPI sensors");
} else { /* I2C sensors on rev v6/7/8 */
CPRINTS("Board using I2C sensors");
/*
* On EVT2, when the sensors are on the same bus as other
* sensors, motion task would not leave enough time for
* processing as soon as its frequency is around ~200Hz.
*/
motion_min_interval = 8 * MSEC;
}
}