static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) { u32 bit = BIT(offset); /* testing on r8a7790 shows that INDT does not show correct pin state * when configured as output, so use OUTDT in case of output pins */ if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit) return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit); else return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit); }
static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) { struct gpio_rcar_priv *p = dev_id; u32 pending; unsigned int offset, irqs_handled = 0; while ((pending = gpio_rcar_read(p, INTDT) & gpio_rcar_read(p, INTMSK))) { offset = __ffs(pending); gpio_rcar_write(p, INTCLR, BIT(offset)); generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); irqs_handled++; } return irqs_handled ? IRQ_HANDLED : IRQ_NONE; }
static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, int bit, bool value) { u32 tmp = gpio_rcar_read(p, offs); if (value) tmp |= BIT(bit); else tmp &= ~BIT(bit); gpio_rcar_write(p, offs, tmp); }
static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long *bits) { struct gpio_rcar_priv *p = gpiochip_get_data(chip); unsigned long flags; u32 val, bankmask; bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); if (chip->valid_mask) bankmask &= chip->valid_mask[0]; if (!bankmask) return; spin_lock_irqsave(&p->lock, flags); val = gpio_rcar_read(p, OUTDT); val &= ~bankmask; val |= (bankmask & bits[0]); gpio_rcar_write(p, OUTDT, val); spin_unlock_irqrestore(&p->lock, flags); }
static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset) { struct gpio_rcar_priv *p = gpiochip_get_data(chip); return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset)); }