static inline void __init overo_init_smsc911x(void)
{
unsigned long cs_mem_base, cs_mem_base2;
/* set up first smsc911x chip */
if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n");
return;
}
overo_smsc911x_resources[0].start = cs_mem_base + 0x0;
overo_smsc911x_resources[0].end = cs_mem_base + 0xff;
if ((gpio_request(OVERO_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
(gpio_direction_input(OVERO_SMSC911X_GPIO) == 0)) {
gpio_export(OVERO_SMSC911X_GPIO, 0);
} else {
printk(KERN_ERR "could not obtain gpio for SMSC911X IRQ\n");
return;
}
overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO);
overo_smsc911x_resources[1].end = 0;
/* set up second smsc911x chip */
if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) {
printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n");
return;
}
overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0;
overo_smsc911x2_resources[0].end = cs_mem_base2 + 0xff;
if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) &&
(gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) {
gpio_export(OVERO_SMSC911X2_GPIO, 0);
} else {
printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n");
return;
}
overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO);
overo_smsc911x2_resources[1].end = 0;
platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices));
}
static inline void __init overo_init_smsc911x(void)
{
unsigned long cs_mem_base;
if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n");
return;
}
overo_smsc911x_resources[0].start = cs_mem_base + 0x0;
overo_smsc911x_resources[0].end = cs_mem_base + 0xff;
if ((gpio_request(OVERO_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
(gpio_direction_input(OVERO_SMSC911X_GPIO) == 0)) {
gpio_export(OVERO_SMSC911X_GPIO, 0);
} else {
printk(KERN_ERR "could not obtain gpio for SMSC911X IRQ\n");
return;
}
overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO);
overo_smsc911x_resources[1].end = 0;
platform_device_register(&overo_smsc911x_device);
}
static inline void __init zoom_init_quaduart(void)
{
int quart_cs;
unsigned long cs_mem_base;
int quart_gpio = 0;
if (gpio_request_one(ZOOM_QUADUART_RST_GPIO,
GPIOF_OUT_INIT_LOW,
"TL16CP754C GPIO") < 0) {
pr_err("Failed to request GPIO%d for TL16CP754C\n",
ZOOM_QUADUART_RST_GPIO);
return;
}
quart_cs = ZOOM_QUADUART_CS;
if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
return;
}
quart_gpio = ZOOM_QUADUART_GPIO;
if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
quart_gpio);
serial_platform_data[0].irq = gpio_to_irq(102);
}
static void __init rx51_init_smc91x(void)
{
int eth_cs;
unsigned long cs_mem_base;
unsigned int rate;
struct clk *l3ck;
eth_cs = RX51_SMC91X_CS;
l3ck = clk_get(NULL, "core_l3_ck");
if (IS_ERR(l3ck))
rate = 100000000;
else
rate = clk_get_rate(l3ck);
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
return;
}
rx51_smc91x_resources[0].start = cs_mem_base + 0x0;
rx51_smc91x_resources[0].end = cs_mem_base + 0xf;
udelay(100);
if (gpio_request(RX51_ETHR_GPIO_IRQ, "SMC91X irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
RX51_ETHR_GPIO_IRQ);
return;
}
gpio_direction_input(RX51_ETHR_GPIO_IRQ);
}
static inline void __init sdp3430_init_smc91x(void)
{
int eth_cs;
unsigned long cs_mem_base;
int eth_gpio = 0;
eth_cs = SDP3430_SMC91X_CS;
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
return;
}
sdp3430_smc91x_resources[0].start = cs_mem_base + 0x0;
sdp3430_smc91x_resources[0].end = cs_mem_base + 0xf;
udelay(100);
if (omap_rev() > OMAP3430_REV_ES1_0)
eth_gpio = OMAP34XX_ETHR_GPIO_IRQ_SDPV2;
else
eth_gpio = OMAP34XX_ETHR_GPIO_IRQ_SDPV1;
sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio);
if (gpio_request(eth_gpio, "SMC91x irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
eth_gpio);
return;
}
gpio_direction_input(eth_gpio);
}
static inline void __init safir_init_smsc911x(void)
{
int eth_cs;
unsigned long cs_mem_base;
int eth_gpio = 0;
omap_mux_init_signal("gpmc_a1", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a2", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a3", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a4", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a5", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a6", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a7", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a8", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a9", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_a10", OMAP_PIN_OUTPUT);
omap_mux_init_signal("gpmc_d8", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d9", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d10", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d11", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d12", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d13", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d14", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_d15", OMAP_PIN_INPUT);
omap_mux_init_signal("gpmc_ncs3", OMAP_PIN_OUTPUT);
omap_mux_init_gpio(SAFIR_SMSC911X_IRQ, OMAP_PIN_INPUT);
omap_mux_init_gpio(SAFIR_SMSC911X_PME, OMAP_PIN_INPUT);
omap_mux_init_gpio(SAFIR_SMSC911X_AMIDX, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(SAFIR_SMSC911X_RESET, OMAP_PIN_OUTPUT);
gpio_init(SAFIR_SMSC911X_AMIDX, 1);
gpio_init(SAFIR_SMSC911X_RESET, 1);
eth_cs = SAFIR_SMSC911X_CS;
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
return;
}
if(gpmc_cs_set_timings(eth_cs, &safir_cs3_gpmc_timings) < 0) {
printk(KERN_ERR "Failed to set gpmc timings\n");
return;
}
safir_smsc911x_resources[0].start = cs_mem_base + 0x0;
safir_smsc911x_resources[0].end = cs_mem_base + 0xff;
eth_gpio = SAFIR_SMSC911X_IRQ;
safir_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
if (gpio_request(eth_gpio, "smsc911x irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
eth_gpio);
return;
}
gpio_direction_input(eth_gpio);
}
static inline void __init apollon_init_smc91x(void)
{
unsigned long base;
/* Make sure CS1 timings are correct */
GPMC_CONFIG1_1 = 0x00011203;
GPMC_CONFIG2_1 = 0x001f1f01;
GPMC_CONFIG3_1 = 0x00080803;
GPMC_CONFIG4_1 = 0x1c091c09;
GPMC_CONFIG5_1 = 0x041f1f1f;
GPMC_CONFIG6_1 = 0x000004c4;
if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
return;
}
apollon_smc91x_resources[0].start = base + 0x300;
apollon_smc91x_resources[0].end = base + 0x30f;
udelay(100);
omap_cfg_reg(W4__24XX_GPIO74);
if (omap_request_gpio(APOLLON_ETHR_GPIO_IRQ) < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
APOLLON_ETHR_GPIO_IRQ);
gpmc_cs_free(APOLLON_ETH_CS);
return;
}
omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
}
static inline void __init zoom2_init_smc911x(void)
{
int eth_cs;
unsigned long cs_mem_base;
int eth_gpio = 0;
eth_cs = LDP_SMC911X_CS;
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc911x\n");
return;
}
zoom2_smc911x_resources[0].start = cs_mem_base + 0x0;
zoom2_smc911x_resources[0].end = cs_mem_base + 0xf;
udelay(100);
eth_gpio = LDP_SMC911X_GPIO;
zoom2_smc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
if (gpio_request(eth_gpio, "smc911x irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc911x IRQ\n",
eth_gpio);
return;
}
gpio_direction_input(eth_gpio);
}
static inline void __init sdp3430_init_smc91x(void)
{
int eth_cs;
unsigned long cs_mem_base;
int eth_gpio = 0;
eth_cs = SDP3430_SMC91X_CS;
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
return;
}
sdp3430_smc91x_resources[0].start = cs_mem_base + 0x0;
sdp3430_smc91x_resources[0].end = cs_mem_base + 0xf;
udelay(100);
if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
eth_gpio = OMAP34XX_ETHR_GPIO_IRQ_SDPV2;
else
eth_gpio = OMAP34XX_ETHR_GPIO_IRQ_SDPV1;
sdp3430_smc91x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
if (omap_request_gpio(eth_gpio) < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
eth_gpio);
return;
}
omap_set_gpio_direction(eth_gpio, 1);
}
static void __init apollon_flash_init(void)
{
unsigned long base;
if (gpmc_cs_request(APOLLON_FLASH_CS, SZ_128K, &base) < 0) {
printk(KERN_ERR "Cannot request OneNAND GPMC CS\n");
return;
}
apollon_flash_resource[0].start = base;
apollon_flash_resource[0].end = base + SZ_128K - 1;
if (gpmc_cs_request(APOLLON_NOR_CS, SZ_32M, &base) < 0) {
printk(KERN_ERR "Cannot request NOR GPMC CS\n");
return;
}
apollon_nor_resource[0].start = base;
apollon_nor_resource[0].end = base + SZ_32M - 1;
}
static inline void __init sdp2430_init_smc91x(void)
{
int eth_cs;
unsigned long cs_mem_base;
unsigned int rate;
struct clk *l3ck;
eth_cs = SDP2430_SMC91X_CS;
l3ck = clk_get(NULL, "core_l3_ck");
if (IS_ERR(l3ck))
rate = 100000000;
else
rate = clk_get_rate(l3ck);
/* Make sure CS1 timings are correct, for 2430 always muxed */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
if (rate >= 160000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else if (rate >= 130000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else { /* rate = 100000000 */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
}
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
return;
}
sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f;
udelay(100);
if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
OMAP24XX_ETHR_GPIO_IRQ);
gpmc_cs_free(eth_cs);
return;
}
omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
}
/*
* Initialize smsc911x device connected to the GPMC. Note that we
* assume that pin multiplexing is done in the board-*.c file,
* or in the bootloader.
*/
void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *gpmc_cfg)
{
struct platform_device *pdev;
unsigned long cs_mem_base;
int ret;
if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
pr_err("Failed to request GPMC mem region\n");
return;
}
gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
goto free1;
}
gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
ret = gpio_request_one(gpmc_cfg->gpio_reset,
GPIOF_OUT_INIT_HIGH, "smsc911x reset");
if (ret) {
pr_err("Failed to request reset GPIO%d\n",
gpmc_cfg->gpio_reset);
goto free2;
}
gpio_set_value(gpmc_cfg->gpio_reset, 0);
msleep(100);
gpio_set_value(gpmc_cfg->gpio_reset, 1);
}
gpmc_smsc911x_config.flags = gpmc_cfg->flags ? : SMSC911X_USE_16BIT;
pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
&gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
if (!pdev) {
pr_err("Unable to register platform device\n");
gpio_free(gpmc_cfg->gpio_reset);
goto free2;
}
return;
free2:
gpio_free(gpmc_cfg->gpio_irq);
free1:
gpmc_cs_free(gpmc_cfg->cs);
pr_err("Could not initialize smsc911x device\n");
}
static void __init h4_init_flash(void)
{
unsigned long base;
if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
printk("Can't request GPMC CS for flash\n");
return;
}
h4_flash_resource.start = base;
h4_flash_resource.end = base + SZ_64M - 1;
}
static int gpmc_config(void)
{
// first reg gpmc_init() already called; io pinmux already configed
// ti8168evm board_nand_init -> gpmc_nand_init
u32 val = 0;
int err = 0;
/*-
EXPORT_SYMBOL(gpmc_cs_write_reg);
EXPORT_SYMBOL(gpmc_cs_read_reg);
EXPORT_SYMBOL(gpmc_cs_set_timings);
-*/
// gpmc cs disable memory
val = gpmc_cs_read_reg(GPMC_FPGA_CS, GPMC_CS_CONFIG7);
val &= ~GPMC_CONFIG7_CSVALID;
gpmc_cs_write_reg(GPMC_FPGA_CS, GPMC_CS_CONFIG7, val);
// disable cs3 irq
gpmc_cs_configure(GPMC_FPGA_CS, GPMC_SET_IRQ_STATUS, 0);
gpmc_cs_configure(GPMC_FPGA_CS, GPMC_ENABLE_IRQ, 0);
// set config1
gpmc_cs_write_reg(GPMC_FPGA_CS, GPMC_CS_CONFIG1, GPMC_CONFIG1_READTYPE_ASYNC| // set read type async
GPMC_CONFIG1_WRITETYPE_ASYNC| // set write type async
GPMC_CONFIG1_DEVICESIZE_16| // set device size 16bit
GPMC_CONFIG1_DEVICETYPE_NOR // set device type nor
);
val = gpmc_cs_read_reg(GPMC_FPGA_CS, GPMC_CS_CONFIG1);
val &= ~GPMC_CONFIG1_MUXADDDATA;
gpmc_cs_write_reg(GPMC_FPGA_CS, GPMC_CS_CONFIG1, val);
// set gpmc timings
err = gpmc_cs_set_timings(GPMC_FPGA_CS, &fpga_timings);
if(err < 0){
printk(KERN_ERR "Unable to set gpmc timings\n");
}
// apply gpmc select memory
err = gpmc_cs_request(GPMC_FPGA_CS, GPMC_FIFO_SIZE, &gpmc_membase);
if(err < 0){
printk(KERN_ERR "Cannot request GPMC CS\n");
return err;
}
// request_mem_region(gpmc_membase, GPMC_FIFO_SIZE, DRIVERNAME);
// fpga_membase = ioremap(gpmc_membase, GPMC_FIFO_SIZE);
return err;
}
int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
{
int err = 0;
struct device *dev = &gpmc_nand_device.dev;
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
(unsigned long *)&gpmc_nand_resource[0].start);
if (err < 0) {
dev_err(dev, "Cannot request GPMC CS\n");
return err;
}
gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
NAND_IO_SIZE - 1;
gpmc_nand_resource[1].start =
gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
gpmc_nand_resource[2].start =
gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
/* Set timings in GPMC */
err = omap2_nand_gpmc_retime(gpmc_nand_data);
if (err < 0) {
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
return err;
}
/* Enable RD PIN Monitoring Reg */
if (gpmc_nand_data->dev_ready) {
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
}
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
err = platform_device_register(&gpmc_nand_device);
if (err < 0) {
dev_err(dev, "Unable to register NAND device\n");
goto out_free_cs;
}
return 0;
out_free_cs:
gpmc_cs_free(gpmc_nand_data->cs);
return err;
}
int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
{
unsigned int val;
int err = 0;
struct device *dev = &gpmc_nand_device.dev;
gpmc_nand_data = _nand_data;
gpmc_nand_data->nand_setup = gpmc_nand_setup;
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
&gpmc_nand_data->phys_base);
if (err < 0) {
dev_err(dev, "Cannot request GPMC CS\n");
return err;
}
err = gpmc_nand_setup();
if (err < 0) {
dev_err(dev, "NAND platform setup failed: %d\n", err);
return err;
}
/* Enable RD PIN Monitoring Reg */
if (gpmc_nand_data->dev_ready) {
val = gpmc_cs_read_reg(gpmc_nand_data->cs,
GPMC_CS_CONFIG1);
val |= WR_RD_PIN_MONITORING;
gpmc_cs_write_reg(gpmc_nand_data->cs,
GPMC_CS_CONFIG1, val);
}
err = platform_device_register(&gpmc_nand_device);
if (err < 0) {
dev_err(dev, "Unable to register NAND device\n");
goto out_free_cs;
}
return 0;
out_free_cs:
gpmc_cs_free(gpmc_nand_data->cs);
return err;
}
/* Map registers to GPMC CS3 */
static inline void __init zoom2_init_quaduart(void)
{
int quart_cs;
unsigned long cs_mem_base;
int quart_gpio = 0;
quart_cs = 3;
if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem"
"for Quad UART(TL16CP754C)\n");
return;
}
quart_gpio = 102;
if (gpio_request(quart_gpio, "quart") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
quart_gpio);
return;
}
gpio_direction_input(quart_gpio);
}
int gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)
{
int err;
struct device *dev = &gpmc_onenand_device.dev;
gpmc_onenand_data = _onenand_data;
gpmc_onenand_data->onenand_setup = gpmc_onenand_setup;
gpmc_onenand_device.dev.platform_data = gpmc_onenand_data;
if (cpu_is_omap24xx() &&
(gpmc_onenand_data->flags & ONENAND_SYNC_READWRITE)) {
dev_warn(dev, "OneNAND using only SYNC_READ on 24xx\n");
gpmc_onenand_data->flags &= ~ONENAND_SYNC_READWRITE;
gpmc_onenand_data->flags |= ONENAND_SYNC_READ;
}
if (cpu_is_omap34xx())
gpmc_onenand_data->flags |= ONENAND_IN_OMAP34XX;
else
gpmc_onenand_data->flags &= ~ONENAND_IN_OMAP34XX;
err = gpmc_cs_request(gpmc_onenand_data->cs, ONENAND_IO_SIZE,
(unsigned long *)&gpmc_onenand_resource.start);
if (err < 0) {
dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
gpmc_onenand_data->cs, err);
return err;
}
gpmc_onenand_resource.end = gpmc_onenand_resource.start +
ONENAND_IO_SIZE - 1;
err = platform_device_register(&gpmc_onenand_device);
if (err) {
dev_err(dev, "Unable to register OneNAND device\n");
gpmc_cs_free(gpmc_onenand_data->cs);
}
return err;
}
static void __init cm_t35_init_smsc911x(void)
{
unsigned long cs_mem_base;
if (gpmc_cs_request(CM_T35_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
pr_err("CM-T35: Failed request for GPMC mem for smsc911x\n");
return;
}
cm_t35_smsc911x_resources[0].start = cs_mem_base + 0x0;
cm_t35_smsc911x_resources[0].end = cs_mem_base + 0xff;
if ((gpio_request(CM_T35_SMSC911X_GPIO, "CM ETH IRQ") == 0) &&
(gpio_direction_input(CM_T35_SMSC911X_GPIO) == 0)) {
gpio_export(CM_T35_SMSC911X_GPIO, 0);
} else {
pr_err("CM-T35: could not obtain gpio for SMSC911X IRQ\n");
return;
}
platform_device_register(&cm_t35_smsc911x_device);
}
int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
{
int err = 0;
struct device *dev = &gpmc_nand_device.dev;
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
&gpmc_nand_data->phys_base);
if (err < 0) {
dev_err(dev, "Cannot request GPMC CS\n");
return err;
}
/* Set timings in GPMC */
err = omap2_nand_gpmc_retime(gpmc_nand_data);
if (err < 0) {
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
return err;
}
/* Enable RD PIN Monitoring Reg */
if (gpmc_nand_data->dev_ready) {
gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_RDY_BSY, 1);
}
err = platform_device_register(&gpmc_nand_device);
if (err < 0) {
dev_err(dev, "Unable to register NAND device\n");
goto out_free_cs;
}
return 0;
out_free_cs:
gpmc_cs_free(gpmc_nand_data->cs);
return err;
}
static inline void __init igep2_init_smsc911x(void)
{
unsigned long cs_mem_base;
if (gpmc_cs_request(IGEP2_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
pr_err("IGEP v2: Failed request for GPMC mem for smsc911x\n");
gpmc_cs_free(IGEP2_SMSC911X_CS);
return;
}
igep2_smsc911x_resources[0].start = cs_mem_base + 0x0;
igep2_smsc911x_resources[0].end = cs_mem_base + 0xff;
if ((gpio_request(IGEP2_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
(gpio_direction_input(IGEP2_SMSC911X_GPIO) == 0)) {
gpio_export(IGEP2_SMSC911X_GPIO, 0);
} else {
pr_err("IGEP v2: Could not obtain gpio for for SMSC911X IRQ\n");
return;
}
platform_device_register(&igep2_smsc911x_device);
}
static void __init cm_t35_init_smsc911x(struct platform_device *dev,
int cs, int irq_gpio)
{
unsigned long cs_mem_base;
if (gpmc_cs_request(cs, SZ_16M, &cs_mem_base) < 0) {
pr_err("CM-T35: Failed request for GPMC mem for smsc911x\n");
return;
}
dev->resource[0].start = cs_mem_base + 0x0;
dev->resource[0].end = cs_mem_base + 0xff;
if ((gpio_request(irq_gpio, "ETH IRQ") == 0) &&
(gpio_direction_input(irq_gpio) == 0)) {
gpio_export(irq_gpio, 0);
} else {
pr_err("CM-T35: could not obtain gpio for SMSC911X IRQ\n");
return;
}
platform_device_register(dev);
}
static int __devinit omap2_onenand_probe(struct platform_device *pdev)
{
struct omap_onenand_platform_data *pdata;
struct omap2_onenand *c;
int r;
pdata = pdev->dev.platform_data;
if (pdata == NULL) {
dev_err(&pdev->dev, "platform data missing\n");
return -ENODEV;
}
c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
if (!c)
return -ENOMEM;
init_completion(&c->irq_done);
init_completion(&c->dma_done);
c->gpmc_cs = pdata->cs;
c->gpio_irq = pdata->gpio_irq;
c->dma_channel = pdata->dma_channel;
if (c->dma_channel < 0) {
c->gpio_irq = 0;
}
r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
if (r < 0) {
dev_err(&pdev->dev, "Cannot request GPMC CS\n");
goto err_kfree;
}
if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
pdev->dev.driver->name) == NULL) {
dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
"size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
r = -EBUSY;
goto err_free_cs;
}
c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
if (c->onenand.base == NULL) {
r = -ENOMEM;
goto err_release_mem_region;
}
if (pdata->onenand_setup != NULL) {
r = pdata->onenand_setup(c->onenand.base, c->freq);
if (r < 0) {
dev_err(&pdev->dev, "Onenand platform setup failed: "
"%d\n", r);
goto err_iounmap;
}
c->setup = pdata->onenand_setup;
}
if (c->gpio_irq) {
if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
dev_err(&pdev->dev, "Failed to request GPIO%d for "
"OneNAND\n", c->gpio_irq);
goto err_iounmap;
}
gpio_direction_input(c->gpio_irq);
if ((r = request_irq(gpio_to_irq(c->gpio_irq),
omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
pdev->dev.driver->name, c)) < 0)
goto err_release_gpio;
}
if (c->dma_channel >= 0) {
r = omap_request_dma(0, pdev->dev.driver->name,
omap2_onenand_dma_cb, (void *) c,
&c->dma_channel);
if (r == 0) {
omap_set_dma_write_mode(c->dma_channel,
OMAP_DMA_WRITE_NON_POSTED);
omap_set_dma_src_data_pack(c->dma_channel, 1);
omap_set_dma_src_burst_mode(c->dma_channel,
OMAP_DMA_DATA_BURST_8);
omap_set_dma_dest_data_pack(c->dma_channel, 1);
omap_set_dma_dest_burst_mode(c->dma_channel,
OMAP_DMA_DATA_BURST_8);
} else {
dev_info(&pdev->dev,
"failed to allocate DMA for OneNAND, "
"using PIO instead\n");
c->dma_channel = -1;
}
}
dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
"base %p\n", c->gpmc_cs, c->phys_base,
c->onenand.base);
c->pdev = pdev;
c->mtd.name = dev_name(&pdev->dev);
c->mtd.priv = &c->onenand;
c->mtd.owner = THIS_MODULE;
c->mtd.dev.parent = &pdev->dev;
if (c->dma_channel >= 0) {
struct onenand_chip *this = &c->onenand;
this->wait = omap2_onenand_wait;
if (cpu_is_omap34xx()) {
this->read_bufferram = omap3_onenand_read_bufferram;
this->write_bufferram = omap3_onenand_write_bufferram;
} else {
this->read_bufferram = omap2_onenand_read_bufferram;
this->write_bufferram = omap2_onenand_write_bufferram;
}
}
if ((r = onenand_scan(&c->mtd, 1)) < 0)
goto err_release_dma;
switch ((c->onenand.version_id >> 4) & 0xf) {
case 0:
c->freq = 40;
break;
case 1:
c->freq = 54;
break;
case 2:
c->freq = 66;
break;
case 3:
c->freq = 83;
break;
}
#ifdef CONFIG_MTD_PARTITIONS
if (pdata->parts != NULL)
r = add_mtd_partitions(&c->mtd, pdata->parts,
pdata->nr_parts);
else
#endif
r = add_mtd_device(&c->mtd);
if (r < 0)
goto err_release_onenand;
platform_set_drvdata(pdev, c);
return 0;
err_release_onenand:
onenand_release(&c->mtd);
err_release_dma:
if (c->dma_channel != -1)
omap_free_dma(c->dma_channel);
if (c->gpio_irq)
free_irq(gpio_to_irq(c->gpio_irq), c);
err_release_gpio:
if (c->gpio_irq)
gpio_free(c->gpio_irq);
err_iounmap:
iounmap(c->onenand.base);
err_release_mem_region:
release_mem_region(c->phys_base, ONENAND_IO_SIZE);
err_free_cs:
gpmc_cs_free(c->gpmc_cs);
err_kfree:
kfree(c);
return r;
}
/* this may be called only from board-*.c setup code */
int __init
tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
unsigned ps_refclk, unsigned waitpin,
unsigned async, unsigned sync,
unsigned irq, unsigned dmachan)
{
int status;
static char error[] __initdata =
KERN_ERR "tusb6010 init error %d, %d\n";
/* ASYNC region, primarily for PIO */
status = gpmc_cs_request(async, SZ_16M, (unsigned long *)
&tusb_resources[0].start);
if (status < 0) {
printk(error, 1, status);
return status;
}
tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
tusb_async.wait_pin = waitpin;
async_cs = async;
status = gpmc_cs_program_settings(async_cs, &tusb_async);
if (status < 0)
return status;
/* SYNC region, primarily for DMA */
status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
&tusb_resources[1].start);
if (status < 0) {
printk(error, 2, status);
return status;
}
tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
tusb_sync.wait_pin = waitpin;
sync_cs = sync;
status = gpmc_cs_program_settings(sync_cs, &tusb_sync);
if (status < 0)
return status;
/* IRQ */
status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
if (status < 0) {
printk(error, 3, status);
return status;
}
tusb_resources[2].start = gpio_to_irq(irq);
/* set up memory timings ... can speed them up later */
if (!ps_refclk) {
printk(error, 4, status);
return -ENODEV;
}
refclk_psec = ps_refclk;
status = tusb6010_platform_retime(1);
if (status < 0) {
printk(error, 5, status);
return status;
}
/* finish device setup ... */
if (!data) {
printk(error, 6, status);
return -ENODEV;
}
tusb_device.dev.platform_data = data;
/* REVISIT let the driver know what DMA channels work */
if (!dmachan)
tusb_device.dev.dma_mask = NULL;
else {
/* assume OMAP 2420 ES2.0 and later */
if (dmachan & (1 << 0))
omap_mux_init_signal("sys_ndmareq0", 0);
if (dmachan & (1 << 1))
omap_mux_init_signal("sys_ndmareq1", 0);
if (dmachan & (1 << 2))
omap_mux_init_signal("sys_ndmareq2", 0);
if (dmachan & (1 << 3))
omap_mux_init_signal("sys_ndmareq3", 0);
if (dmachan & (1 << 4))
omap_mux_init_signal("sys_ndmareq4", 0);
if (dmachan & (1 << 5))
omap_mux_init_signal("sys_ndmareq5", 0);
}
/* so far so good ... register the device */
status = platform_device_register(&tusb_device);
if (status < 0) {
printk(error, 7, status);
return status;
}
return 0;
}
/*
* Initialize smc91x device connected to the GPMC. Note that we
* assume that pin multiplexing is done in the board-*.c file,
* or in the bootloader.
*/
void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
{
unsigned long cs_mem_base;
int ret;
gpmc_cfg = board_data;
if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96)
gpmc_cfg->retime = smc91c96_gpmc_retime;
if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
return;
}
gpmc_smc91x_resources[0].start = cs_mem_base + 0x300;
gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
smc91x_settings.mux_add_data = GPMC_MUX_AD;
if (gpmc_cfg->flags & GPMC_READ_MON)
smc91x_settings.wait_on_read = true;
if (gpmc_cfg->flags & GPMC_WRITE_MON)
smc91x_settings.wait_on_write = true;
if (gpmc_cfg->wait_pin)
smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
if (ret < 0)
goto free1;
if (gpmc_cfg->retime) {
ret = gpmc_cfg->retime();
if (ret != 0)
goto free1;
}
if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "SMC91X irq") < 0)
goto free1;
gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
if (gpmc_cfg->gpio_pwrdwn) {
ret = gpio_request_one(gpmc_cfg->gpio_pwrdwn,
GPIOF_OUT_INIT_LOW, "SMC91X powerdown");
if (ret)
goto free2;
}
if (gpmc_cfg->gpio_reset) {
ret = gpio_request_one(gpmc_cfg->gpio_reset,
GPIOF_OUT_INIT_LOW, "SMC91X reset");
if (ret)
goto free3;
gpio_set_value(gpmc_cfg->gpio_reset, 1);
msleep(100);
gpio_set_value(gpmc_cfg->gpio_reset, 0);
}
if (platform_device_register(&gpmc_smc91x_device) < 0) {
printk(KERN_ERR "Unable to register smc91x device\n");
gpio_free(gpmc_cfg->gpio_reset);
goto free3;
}
return;
free3:
if (gpmc_cfg->gpio_pwrdwn)
gpio_free(gpmc_cfg->gpio_pwrdwn);
free2:
gpio_free(gpmc_cfg->gpio_irq);
free1:
gpmc_cs_free(gpmc_cfg->cs);
printk(KERN_ERR "Could not initialize smc91x\n");
}
static inline void __init h4_init_debug(void)
{
int eth_cs;
unsigned long cs_mem_base;
unsigned int muxed, rate;
struct clk *gpmc_fck;
eth_cs = H4_SMC91X_CS;
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
if (IS_ERR(gpmc_fck)) {
WARN_ON(1);
return;
}
clk_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
clk_disable(gpmc_fck);
clk_put(gpmc_fck);
if (is_gpmc_muxed())
muxed = 0x200;
else
muxed = 0;
/* Make sure CS1 timings are correct */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
0x00011000 | muxed);
if (rate >= 160000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else if (rate >= 130000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else {/* rate = 100000000 */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
}
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
goto out;
}
udelay(100);
omap_mux_init_gpio(92, 0);
if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0)
gpmc_cs_free(eth_cs);
out:
clk_disable(gpmc_fck);
clk_put(gpmc_fck);
}
static inline void __init apollon_init_smc91x(void)
{
unsigned long base;
unsigned int rate;
struct clk *gpmc_fck;
int eth_cs;
int err;
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
if (IS_ERR(gpmc_fck)) {
WARN_ON(1);
return;
}
clk_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
eth_cs = APOLLON_ETH_CS;
/* Make sure CS1 timings are correct */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
if (rate >= 160000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else if (rate >= 130000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else {/* rate = 100000000 */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
}
if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
goto out;
}
apollon_smc91x_resources[0].start = base + 0x300;
apollon_smc91x_resources[0].end = base + 0x30f;
udelay(100);
omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0);
err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq");
if (err) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
APOLLON_ETHR_GPIO_IRQ);
gpmc_cs_free(APOLLON_ETH_CS);
}
out:
clk_disable(gpmc_fck);
clk_put(gpmc_fck);
}
/* this may be called only from board-*.c setup code */
int __init
tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
unsigned ps_refclk, unsigned waitpin,
unsigned async, unsigned sync,
unsigned irq, unsigned dmachan)
{
int status;
static char error[] __initdata =
KERN_ERR "tusb6010 init error %d, %d\n";
/* ASYNC region, primarily for PIO */
status = gpmc_cs_request(async, SZ_16M, (unsigned long *)
&tusb_resources[0].start);
if (status < 0) {
printk(error, 1, status);
return status;
}
tusb_resources[0].end = tusb_resources[0].start + 0x9ff;
async_cs = async;
gpmc_cs_write_reg(async, GPMC_CS_CONFIG1,
GPMC_CONFIG1_PAGE_LEN(2)
| GPMC_CONFIG1_WAIT_READ_MON
| GPMC_CONFIG1_WAIT_WRITE_MON
| GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
| GPMC_CONFIG1_READTYPE_ASYNC
| GPMC_CONFIG1_WRITETYPE_ASYNC
| GPMC_CONFIG1_DEVICESIZE_16
| GPMC_CONFIG1_DEVICETYPE_NOR
| GPMC_CONFIG1_MUXADDDATA);
/* SYNC region, primarily for DMA */
status = gpmc_cs_request(sync, SZ_16M, (unsigned long *)
&tusb_resources[1].start);
if (status < 0) {
printk(error, 2, status);
return status;
}
tusb_resources[1].end = tusb_resources[1].start + 0x9ff;
sync_cs = sync;
gpmc_cs_write_reg(sync, GPMC_CS_CONFIG1,
GPMC_CONFIG1_READMULTIPLE_SUPP
| GPMC_CONFIG1_READTYPE_SYNC
| GPMC_CONFIG1_WRITEMULTIPLE_SUPP
| GPMC_CONFIG1_WRITETYPE_SYNC
| GPMC_CONFIG1_CLKACTIVATIONTIME(1)
| GPMC_CONFIG1_PAGE_LEN(2)
| GPMC_CONFIG1_WAIT_READ_MON
| GPMC_CONFIG1_WAIT_WRITE_MON
| GPMC_CONFIG1_WAIT_PIN_SEL(waitpin)
| GPMC_CONFIG1_DEVICESIZE_16
| GPMC_CONFIG1_DEVICETYPE_NOR
| GPMC_CONFIG1_MUXADDDATA
/* fclk divider gets set later */
);
/* IRQ */
status = gpio_request(irq, "TUSB6010 irq");
if (status < 0) {
printk(error, 3, status);
return status;
}
gpio_direction_input(irq);
tusb_resources[2].start = irq + IH_GPIO_BASE;
/* set up memory timings ... can speed them up later */
if (!ps_refclk) {
printk(error, 4, status);
return -ENODEV;
}
refclk_psec = ps_refclk;
status = tusb6010_platform_retime(1);
if (status < 0) {
printk(error, 5, status);
return status;
}
/* finish device setup ... */
if (!data) {
printk(error, 6, status);
return -ENODEV;
}
tusb_device.dev.platform_data = data;
/* REVISIT let the driver know what DMA channels work */
if (!dmachan)
tusb_device.dev.dma_mask = NULL;
else {
/* assume OMAP 2420 ES2.0 and later */
if (dmachan & (1 << 0))
omap_cfg_reg(AA10_242X_DMAREQ0);
if (dmachan & (1 << 1))
omap_cfg_reg(AA6_242X_DMAREQ1);
if (dmachan & (1 << 2))
omap_cfg_reg(E4_242X_DMAREQ2);
if (dmachan & (1 << 3))
omap_cfg_reg(G4_242X_DMAREQ3);
if (dmachan & (1 << 4))
omap_cfg_reg(D3_242X_DMAREQ4);
if (dmachan & (1 << 5))
omap_cfg_reg(E3_242X_DMAREQ5);
}
/* so far so good ... register the device */
status = platform_device_register(&tusb_device);
if (status < 0) {
printk(error, 7, status);
return status;
}
return 0;
}
static inline void __init sdp2430_init_smc91x(void)
{
int eth_cs;
unsigned long cs_mem_base;
unsigned int rate;
struct clk *gpmc_fck;
eth_cs = SDP2430_SMC91X_CS;
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
if (IS_ERR(gpmc_fck)) {
WARN_ON(1);
return;
}
clk_enable(gpmc_fck);
rate = clk_get_rate(gpmc_fck);
/* Make sure CS1 timings are correct, for 2430 always muxed */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
if (rate >= 160000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else if (rate >= 130000000) {
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
} else { /* rate = 100000000 */
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
}
if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
goto out;
}
sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f;
udelay(100);
if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
OMAP24XX_ETHR_GPIO_IRQ);
gpmc_cs_free(eth_cs);
goto out;
}
gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ);
out:
clk_disable(gpmc_fck);
clk_put(gpmc_fck);
}
int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
struct gpmc_timings *gpmc_t)
{
int err = 0;
struct gpmc_settings s;
struct platform_device *pdev;
struct resource gpmc_nand_res[] = {
{ .flags = IORESOURCE_MEM, },
{ .flags = IORESOURCE_IRQ, },
{ .flags = IORESOURCE_IRQ, },
};
BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM);
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
(unsigned long *)&gpmc_nand_res[0].start);
if (err < 0) {
pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n",
gpmc_nand_data->cs, err);
return err;
}
gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1;
gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
if (gpmc_t) {
err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
if (err < 0) {
pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err);
return err;
}
