void
hal_init(void)
{
/*Reset variables used in file.*/
hal_system_time = 0;
// hal_reset_flags();
/*IO Specific Initialization - sleep and reset pins. */
DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
DDR_RST |= (1 << RST); /* Enable RST as output. */
/*SPI Specific Initialization.*/
/* Set SS, CLK and MOSI as output. */
HAL_DDR_SS |= (1 << HAL_SS_PIN);
HAL_DDR_SCK |= (1 << HAL_SCK_PIN);
HAL_DDR_MOSI |= (1 << HAL_MOSI_PIN);
HAL_DDR_MISO &= ~(1 << HAL_MISO_PIN);
/* Set SS */
HAL_PORT_SS |= (1 << HAL_SS_PIN); // HAL_SS_HIGH()
HAL_PORT_SCK &= ~(1 << HAL_SCK_PIN); // SCLK.clr()
/*TIMER Specific Initialization.*/
// Init count source (Timer B3)
TB3 = ((16*10) - 1); // 16 us ticks
TB3MR.BYTE = 0b00000000; // Timer mode, F1
TBSR.BIT.TB3S = 1; // Start Timer B3
TB4 = 0xFFFF; //
TB4MR.BYTE = 0b10000001; // Counter mode, count TB3
TBSR.BIT.TB4S = 1; // Start Timer B4
INT1IC.BIT.POL = 1; // Select rising edge
HAL_ENABLE_OVERFLOW_INTERRUPT(); /* Enable Timer overflow interrupt. */
hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */
}
void
hal_init(void)
{
/*Reset variables used in file.*/
hal_system_time = 0;
// hal_reset_flags();
/*IO Specific Initialization - sleep and reset pins. */
/* Set pins low before they are initialized as output? Does not seem to matter */
// hal_set_rst_low();
// hal_set_slptr_low();
DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
DDR_RST |= (1 << RST); /* Enable RST as output. */
/*SPI Specific Initialization.*/
/* Set SS, CLK and MOSI as output. */
/* To avoid a SPI glitch, the port register shall be set before the DDR register */
HAL_PORT_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK); /* Set SS and CLK high */
HAL_DDR_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK) | (1 << HAL_DD_MOSI);
HAL_DDR_SPI &=~ (1<< HAL_DD_MISO); /* MISO input */
/* Run SPI at max speed */
SPCR = (1 << SPE) | (1 << MSTR); /* Enable SPI module and master operation. */
SPSR = (1 << SPI2X); /* Enable doubled SPI speed in master mode. */
/*TIMER1 Specific Initialization.*/
TCCR1B = HAL_TCCR1B_CONFIG; /* Set clock prescaler */
TIFR1 |= (1 << ICF1); /* Clear Input Capture Flag. */
HAL_ENABLE_OVERFLOW_INTERRUPT(); /* Enable Timer1 overflow interrupt. */
hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */
}
/** \brief This function initializes the Hardware Abstraction Layer.
*/
void
hal_init(void)
{
/*Reset variables used in file.*/
//GH: not used hal_system_time = 0;
// hal_reset_flags();
/*IO Specific Initialization.*/
DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
DDR_RST |= (1 << RSTPIN); /* Enable RSTPIN as output. */
/*SPI Specific Initialization.*/
/* Set SS, CLK and MOSI as output. */
HAL_DDR_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK) | (1 << HAL_DD_MOSI);
HAL_PORT_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK); /* Set SS and CLK high */
/* Run SPI at max speed */
SPCR = (1 << SPE) | (1 << MSTR); /* Enable SPI module and master operation. */
#ifdef SPIC // for ATxmega control register is used
SPIC_CTRL |= SPI_CLK2X_bm;
#else // for ATmega architecture status register is used
SPSR = (1 << SPI2X); /* Enable doubled SPI speed in master mode. */
#endif
#ifdef TCCR1B // for ATmega architecture Timer 1 is used
/*TIMER1 Specific Initialization.*/
TCCR1B = HAL_TCCR1B_CONFIG; /* Set clock prescaler */
TIFR1 |= (1 << ICF1); /* Clear Input Capture Flag. */
#elif defined(TCC1) // for ATxmega Timer C1 is used
/* Timer specific defines, instead Timer 1 we use Timer C 1*/
TCC1_CTRLA = HAL_TCC1_CTRLA_CONFIG;
TCC1_INTFLAGS = 0xFF;
#endif
HAL_ENABLE_OVERFLOW_INTERRUPT(); /* Enable Timer1 overflow interrupt. */
hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */
}
void
hal_init(void)
{
/*Reset variables used in file.*/
/*IO Specific Initialization - sleep and reset pins. */
/* Set pins low before they are initialized as output? Does not seem to matter */
// hal_set_rst_low();
// hal_set_slptr_low();
DDR_SLP_TR |= (1 << SLP_TR); /* Enable SLP_TR as output. */
DDR_RST |= (1 << RST); /* Enable RST as output. */
/*SPI Specific Initialization.*/
/* Set SS, CLK and MOSI as output. */
/* To avoid a SPI glitch, the port register shall be set before the DDR register */
HAL_PORT_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK); /* Set SS and CLK high */
HAL_DDR_SPI |= (1 << HAL_DD_SS) | (1 << HAL_DD_SCK) | (1 << HAL_DD_MOSI);
HAL_DDR_SPI &=~ (1<< HAL_DD_MISO); /* MISO input */
/* Run SPI at max speed */
SPCR = (1 << SPE) | (1 << MSTR); /* Enable SPI module and master operation. */
SPSR = (1 << SPI2X); /* Enable doubled SPI speed in master mode. */
/* Enable interrupts from the radio transceiver. */
hal_enable_trx_interrupt();
}
void
hal_init(void)
{
/*Reset variables used in file.*/
hal_system_time = 0;
// TCCR1B = HAL_TCCR1B_CONFIG; /* Set clock prescaler */
// TIFR1 |= (1 << ICF1); /* Clear Input Capture Flag. */
// HAL_ENABLE_OVERFLOW_INTERRUPT(); /* Enable Timer1 overflow interrupt. */
hal_enable_trx_interrupt(); /* Enable interrupts from the radio transceiver. */
}
/*! \brief This function initializes the Hardware Abstraction Layer.
*
*/
void hal_init(void)
{
#ifdef SINGLE_CHIP
// do nothing -> there is no external transceiver
DRTRAM0 = _BV(ENDRT);
DRTRAM1 = _BV(ENDRT);
DRTRAM2 = _BV(ENDRT);
DRTRAM3 = _BV(ENDRT);
#else
/*IO Specific Initialization.*/
DDR_SLP_TR |= (1 << SLP_TR); //Enable SLP_TR as output.
DDR_RST |= (1 << RST); //Enable RST as output.
#endif // do nothing
hal_spi_init();
hal_enable_trx_interrupt(); //Enable interrupts from the radio transceiver.
}
