void hal_nrf_close_pipe(hal_nrf_address_t pipe_num)
{
en_pipes_t en_rxaddr;
en_pipes_t en_aa;
en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
en_aa.value = hal_nrf_read_reg (EN_AA);
switch(pipe_num)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
en_rxaddr.value = en_rxaddr.value & (uint8_t)~SET_BIT(pipe_num);
en_aa.value = en_aa.value & (uint8_t)~SET_BIT(pipe_num);
break;
case HAL_NRF_ALL:
en_rxaddr.value = 0U;
en_aa.value = 0U;
break;
case HAL_NRF_TX:
default:
break;
}
hal_nrf_write_reg (EN_RXADDR, en_rxaddr.value);
hal_nrf_write_reg (EN_AA, en_aa.value);
}
void hal_nrf_open_pipe(hal_nrf_address_t pipe_num, bool auto_ack)
{
en_pipes_t en_rxaddr;
en_pipes_t en_aa;
en_rxaddr.value = hal_nrf_read_reg (EN_RXADDR);
en_aa.value = hal_nrf_read_reg (EN_AA);
switch(pipe_num)
{
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
en_rxaddr.value = en_rxaddr.value | SET_BIT(pipe_num);
if(auto_ack)
{
en_aa.value = en_aa.value | SET_BIT(pipe_num);
}
else
{
en_aa.value = en_aa.value & (uint8_t)~SET_BIT(pipe_num);
}
break;
case HAL_NRF_ALL:
en_rxaddr.value = (uint8_t)(~(BIT_6|BIT_7));
if(auto_ack)
{
en_aa.value = (uint8_t)(~(BIT_6|BIT_7));
}
else
{
en_aa.value = 0U;
}
break;
case HAL_NRF_TX:
default:
break;
}
hal_nrf_write_reg (EN_RXADDR, en_rxaddr.value);
hal_nrf_write_reg (EN_AA, en_aa.value);
}
void hal_nrf_setup_dynamic_payload (uint8_t setup)
{
en_pipes_t dynpd;
dynpd.value = setup & (uint8_t)~0xC0U;
hal_nrf_write_reg (DYNPD, dynpd.value);
}
void hal_nrf_set_address_width(hal_nrf_address_width_t aw)
{
setup_aw_t setup_aw;
setup_aw.bits.aw = (uint8_t)aw - 2;
hal_nrf_write_reg (SETUP_AW, setup_aw.value);
}
void hal_nrf_set_rf_channel(uint8_t channel)
{
rf_ch_t rf_ch;
rf_ch.value = 0U;
rf_ch.bits.rf_ch = channel;
hal_nrf_write_reg (RF_CH, rf_ch.value);
}
void hal_nrf_set_pll_mode(bool pll_lock)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
rf_setup.bits.pll_lock = (pll_lock) ? 1U : 0U;
hal_nrf_write_reg(RF_SETUP, rf_setup.value);
}
uint8_t hal_nrf_get_clear_irq_flags(void)
{
uint8_t retval;
retval = hal_nrf_write_reg (STATUS, (BIT_6|BIT_5|BIT_4));
return (retval & (BIT_6|BIT_5|BIT_4));
}
void hal_nrf_enable_continious_wave (bool enable)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
rf_setup.bits.cont_wave = (enable ? 1U : 0U);
hal_nrf_write_reg(RF_SETUP, rf_setup.value);
}
void hal_nrf_enable_dynamic_payload(bool enable)
{
feature_t feature;
feature.value = hal_nrf_read_reg (FEATURE);
feature.bits.en_dpl = (enable) ? 1 : 0;
hal_nrf_write_reg (FEATURE, feature.value);
}
void hal_nrf_enable_ack_payload(bool enable)
{
feature_t feature;
feature.value = hal_nrf_read_reg (FEATURE);
feature.bits.en_ack_pay = (enable) ? 1U : 0U;
hal_nrf_write_reg (FEATURE, feature.value);
}
void hal_nrf_set_auto_retr(uint8_t retr, uint16_t delay)
{
setup_retr_t setup_retr;
setup_retr.bits.ard = (uint8_t)(delay >> 8);
setup_retr.bits.arc = retr;
hal_nrf_write_reg (SETUP_RETR, setup_retr.value);
}
void hal_nrf_enable_dynamic_ack(bool enable)
{
feature_t feature;
feature.value = hal_nrf_read_reg (FEATURE);
feature.bits.en_dyn_ack = (enable) ? 1U : 0U;
hal_nrf_write_reg (FEATURE, feature.value);
}
void hal_nrf_set_output_power(hal_nrf_output_power_t power)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
rf_setup.bits.rf_pwr = (uint8_t)power;
hal_nrf_write_reg (RF_SETUP, rf_setup.value);
}
uint8_t hal_nrf_clear_irq_flags_get_status(void)
{
uint8_t retval;
// When RFIRQ is cleared (when calling write_reg), pipe information is unreliable (read again with read_reg)
retval = hal_nrf_write_reg (STATUS, (BIT_6|BIT_5|BIT_4)) & (BIT_6|BIT_5|BIT_4);
retval |= hal_nrf_read_reg (STATUS) & (BIT_3|BIT_2|BIT_1|BIT_0);
return (retval);
}
void hal_nrf_set_operation_mode(hal_nrf_operation_mode_t op_mode)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
if(op_mode == HAL_NRF_PRX)
{
config.bits.prim_rx = 1U;
}
else
{
config.bits.prim_rx = 0U;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_power_mode(hal_nrf_pwr_mode_t pwr_mode)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
if(pwr_mode == HAL_NRF_PWR_UP)
{
config.bits.pwr_up = 1U;
}
else
{
config.bits.pwr_up = 0U;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_irq_mode(hal_nrf_irq_source_t int_source, bool irq_state)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
switch (int_source)
{
case HAL_NRF_MAX_RT:
config.bits.mask_max_rt = irq_state ? 0U : 1U;
break;
case HAL_NRF_TX_DS:
config.bits.mask_tx_ds = irq_state ? 0U : 1U;
break;
case HAL_NRF_RX_DR:
config.bits.mask_rx_dr = irq_state ? 0U : 1U;
break;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_address(const hal_nrf_address_t address, const uint8_t *addr)
{
switch(address)
{
case HAL_NRF_TX:
case HAL_NRF_PIPE0:
case HAL_NRF_PIPE1:
hal_nrf_write_multibyte_reg(W_REGISTER + RX_ADDR_P0 + (uint8_t) address, addr, hal_nrf_get_address_width());
break;
case HAL_NRF_PIPE2:
case HAL_NRF_PIPE3:
case HAL_NRF_PIPE4:
case HAL_NRF_PIPE5:
hal_nrf_write_reg (RX_ADDR_P0 + (uint8_t) address, *addr);
break;
default:
break;
}
}
void hal_nrf_set_crc_mode(hal_nrf_crc_mode_t crc_mode)
{
config_t config;
config.value = hal_nrf_read_reg (CONFIG);
switch (crc_mode)
{
case HAL_NRF_CRC_OFF:
config.bits.en_crc = 0U;
break;
case HAL_NRF_CRC_8BIT:
config.bits.en_crc = 1U;
config.bits.crc0 = 0U;
break;
case HAL_NRF_CRC_16BIT:
config.bits.en_crc = 1U;
config.bits.crc0 = 1U;
break;
default:
break;
}
hal_nrf_write_reg (CONFIG, config.value);
}
void hal_nrf_set_datarate(hal_nrf_datarate_t datarate)
{
rf_setup_t rf_setup;
rf_setup.value = hal_nrf_read_reg (RF_SETUP);
switch (datarate)
{
case HAL_NRF_250KBPS:
rf_setup.bits.rf_dr_low = 1U;
rf_setup.bits.rf_dr_high = 0U;
break;
case HAL_NRF_1MBPS:
rf_setup.bits.rf_dr_low = 0U;
rf_setup.bits.rf_dr_high = 0U;
break;
case HAL_NRF_2MBPS:
default:
rf_setup.bits.rf_dr_low = 0U;
rf_setup.bits.rf_dr_high = 1U;
break;
}
hal_nrf_write_reg (RF_SETUP, rf_setup.value);
}
__interrupt void HAL_NRF_ISR(void)
{
u8 status, len, i;
if(!IRQ) {
/** */
// Read and clear IRQ flags from radio
status = hal_nrf_nop();
// if(hal_nrf_ack_flag){
// if((status&0x60) == 0x60){
// hal_nrf_ack_flag = 0;
// }else{
// read_flash_buf(slave_cmd, slave_cmd_request, CMD_LENGTH);
// hal_nrf_write_ack_payload(0, slave_cmd, CMD_LENGTH);
// }
// }
#ifdef SLAVE_DEBUG
hal_nrf_irq_flag = status;
#endif
if(status & (1<< (uint8_t)HAL_NRF_RX_DR)){
do{
len = hal_nrf_read_rx_payload_width();
if(len > 32){
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
hal_nrf_rx_sta = HAL_NRF_RX_STA_COM_ERROR;
return;
}
if((hal_nrf_rx_cnt + len + 1) < HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_buf[hal_nrf_rx_wr_index] = len;
hal_nrf_rx_wr_index++;
if(hal_nrf_rx_wr_index == HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_wr_index=0;
}
// hal_nrf_read_payload((u8*)hal_nrf_rx_buf[hal_nrf_rx_wr_index].buf, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(R_RX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(0U);
while(HAL_NRF_HW_SPI_BUSY){}
hal_nrf_rx_buf[hal_nrf_rx_wr_index] = HAL_NRF_HW_SPI_READ();
hal_nrf_rx_wr_index++;
if(hal_nrf_rx_wr_index == HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_wr_index=0;
}
}
CSN_HIGH();
hal_nrf_rx_cnt = hal_nrf_rx_cnt+len+1;
}else{
hal_nrf_flush_rx();
hal_nrf_rx_sta = HAL_NRF_RX_STA_BUF_OVF;
/** clear RX_DR */
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
break;
}
/** clear RX_DR */
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
}while(!hal_nrf_rx_fifo_empty());
}
if(status & (1 << (uint8_t)HAL_NRF_TX_DS)){
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_TX_DS));
switch(hal_nrf_sta){
case HAL_NRF_STA_TX:
hal_nrf_tx_cmd_flag = 0;
if(hal_nrf_tx_cnt){
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
if(hal_nrf_tx_sta == HAL_NRF_TX_STA_IDLE){
/** send end pkt */
hal_nrf_tx_sta = HAL_NRF_TX_STA_DONE;
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_write_tx_payload(slave_cmd, CMD_LENGTH);
hal_nrf_tx_cmd_flag = 2;
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
}
}
break;
case HAL_NRF_STA_RX:
/** ack payload send */
break;
case HAL_NRF_STA_TX_CMD:
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
hal_nrf_tx_cmd_flag = 0;
break;
}
}
if(status & (1 << (uint8_t)HAL_NRF_MAX_RT)){
#if 0
// When a MAX_RT interrupt occurs the TX payload will not be removed from the TX FIFO.
// If the packet is to be discarded this must be done manually by flushing the TX FIFO.
// Alternatively, CE_PULSE() can be called re-starting transmission of the payload.
// (Will only be possible after the radio irq flags are cleared)
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_sta=HAL_NRF_STA_RX;
/** discard all data in buffer */
hal_nrf_tx_busy = 0;
hal_nrf_tx_cnt = 0;
hal_nrf_tx_rd_index =0;
hal_nrf_tx_wr_index = 0;
// hal_nrf_flush_rx();
// hal_nrf_rx_cnt = 0;
// hal_nrf_rx_rd_index =0;
// hal_nrf_rx_wr_index = 0;
/** set timeout flag */
hal_nrf_timeout = 1;
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_MAX_RT));
#else
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_MAX_RT));
switch(hal_nrf_sta){
case HAL_NRF_STA_TX:
hal_nrf_tx_cmd_flag = 0;
if(hal_nrf_tx_cnt){
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
if(hal_nrf_tx_sta == HAL_NRF_TX_STA_IDLE){
/** send end pkt */
hal_nrf_tx_sta = HAL_NRF_TX_STA_DONE;
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_write_tx_payload(slave_cmd, CMD_LENGTH);
hal_nrf_tx_cmd_flag = 2;
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
}
}
break;
case HAL_NRF_STA_RX:
/** ack payload send */
break;
case HAL_NRF_STA_TX_CMD:
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
hal_nrf_tx_cmd_flag = 0;
break;
}
#endif
}
}
}
void main(void) {
int i = 0; // local counter
int total_pkt_count = 1;
int addr_width = 5;
int customized_plen = 0;
int pipe_num = 6;
epl_rf_en_auto_ack_t auto_ack = 0;
//int mode = 1; // 1 for sender mode, 2 for dumper mode
// new params
unsigned char pipe_source; // used to store pipe_source number
unsigned char ACKbuf[] = "ACK";
unsigned char temp_buf[34]; // used for dumper to get RF packets from RX FIFO
unsigned char temp_addr[5];
unsigned char data_length = 0;
unsigned char dynpd_pipe;
unsigned char addr_buf[5];
// set pin direction
P0EXP = 0x00;
P0ALT = 0x00;
P0DIR = 0x00;
// uart init
epl_uart_init(UART_BAUD_57K6);
//init usb connection
usb_init(); // Initialize USB
EA = 1; // Enable global IRQ
//Start RF tx mode
epl_rf_en_quick_init(cfg);
//Clear TX FIFO
hal_nrf_write_reg(FLUSH_TX, 0);
hal_nrf_write_reg(FLUSH_RX, 0);
hal_nrf_lock_unlock();
hal_nrf_enable_dynamic_pl();
LED_Blink(20);
epl_uart_putstr("start!");
while (1) {
usb_recv_packet();
switch (ubuf[1]) {
case EPL_SENDER_MODE:
customized_plen = 0;
for (i = 0; i < PLOAD_LEN; i++)
packet[i] = i + 9;
hal_nrf_close_pipe(HAL_NRF_PIPE1);
hal_nrf_close_pipe(HAL_NRF_PIPE2);
hal_nrf_close_pipe(HAL_NRF_PIPE3);
hal_nrf_close_pipe(HAL_NRF_PIPE4);
hal_nrf_close_pipe(HAL_NRF_PIPE5);
break;
case EPL_DUMPER_MODE:
hal_nrf_close_pipe(HAL_NRF_PIPE1);
hal_nrf_close_pipe(HAL_NRF_PIPE2);
hal_nrf_close_pipe(HAL_NRF_PIPE3);
hal_nrf_close_pipe(HAL_NRF_PIPE4);
hal_nrf_close_pipe(HAL_NRF_PIPE5);
break;
case EPL_OUTPUT_POWER: //Host:set_output_power
hal_nrf_set_output_power(ubuf[2]);
epl_uart_putstr("EPL_OUTPUT_POWER\n");
usb_send_packet(ACKbuf, 3);
epl_uart_putstr("EPL_OUTPUT_POWER END\n");
break;
case EPL_CHANNEL:
hal_nrf_set_rf_channel(ubuf[2]);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATARATE:
hal_nrf_set_datarate(ubuf[2]);
usb_send_packet(ACKbuf, 3);
break;
case EPL_ADDR_WIDTH:
addr_width = (int) ubuf[2];
hal_nrf_set_address_width(ubuf[2]);
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P0:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P1:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P2:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P3:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P4:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_AUTOACK_P5:
auto_ack = ubuf[2];
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P0:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE0, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P1:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE1, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P2:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE2, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P3:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE3, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P4:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE4, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_DATA_LENGTH_P5:
data_length = (int) ubuf[2];
epl_rf_en_rcv_pipe_config(HAL_NRF_PIPE5, temp_addr, data_length, auto_ack);
usb_send_packet(ACKbuf, 3);
break;
case EPL_CRC_MODE:
if (ubuf[2] == 0)
hal_nrf_set_crc_mode(HAL_NRF_CRC_OFF);
else if (ubuf[2] == 2)
hal_nrf_set_crc_mode(HAL_NRF_CRC_8BIT);
else if (ubuf[2] == 3)
hal_nrf_set_crc_mode(HAL_NRF_CRC_16BIT);
else
;
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P0:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
hal_nrf_set_address(HAL_NRF_PIPE0, temp_addr);
epl_rf_en_set_dst_addr(temp_addr);
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P1:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P2:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P3:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P4:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_RX_ADDR_P5:
for (i = 0; i < addr_width; i++) {
temp_addr[i] = ubuf[i + 2];
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_USER_PLOAD:
if (ubuf[2] == USRS_PLOAD) {
customized_plen = (int) ubuf[3];
for (i = 0; i < customized_plen; i++) {
packet[i] = ubuf[i + 4];
}
} else {
customized_plen = 0;
for (i = 0; i < PLOAD_LEN; i++) {
packet[i] = i + 9;
}
}
usb_send_packet(ACKbuf, 3);
break;
case EPL_NEW_COUNTER:
total_pkt_count = 1;
usb_send_packet(ACKbuf, 3);
break;
/*20110221 celine*/
case EPL_DYNAMIC_PD:
dynpd_pipe = (int)ubuf[2];
if ((int)ubuf[3] == 01){
//hal_nrf_setup_dyn_pl(dynpd_pipe);
hal_nrf_write_reg(DYNPD, (1<<dynpd_pipe) | hal_nrf_read_reg(DYNPD));
} else {
//hal_nrf_lock_unlock();
//hal_nrf_enable_dynamic_pl();
hal_nrf_write_reg(DYNPD, ~(1<<dynpd_pipe) & hal_nrf_read_reg(DYNPD));
}
usb_send_packet(ACKbuf, 3);
break;
/**/
case EPL_RUN_SENDER:
epl_rf_en_enter_tx_mode();
// clear Tx irq
hal_nrf_clear_irq_flag(HAL_NRF_TX_DS);
hal_nrf_clear_irq_flag(HAL_NRF_MAX_RT);
if (ubuf[2] == AUTO_PLOAD) {
epl_uart_putstr("\nauto pload\r\n");
packet[0] = total_pkt_count++;
epl_rf_en_send(packet, data_length);
} else {
epl_uart_putstr("\nusrs pload\r\n");
epl_rf_en_send(packet, customized_plen);
}
LED_Blink(10);
array_cp(temp_buf, ACKbuf, 3);
temp_buf[3] = hal_nrf_read_reg(OBSERVE_TX) & 0x0F;
usb_send_packet(temp_buf, 4);
epl_rf_en_enter_rx_mode();
break;
case EPL_RUN_DUMPER:
hal_nrf_clear_irq_flag(HAL_NRF_RX_DR);
hal_nrf_flush_rx();
epl_rf_en_enter_rx_mode();
while (1) {
if (ubuf[1] == 0xf5) { // Host wants to terminate
epl_uart_putstr("Terminate !\r\n");
break;
}else if (hal_nrf_rx_fifo_empty() == 0) { // Rx_fifo is not empty
LED0_Toggle();
pipe_source = hal_nrf_get_rx_data_source();
hal_nrf_read_rx_pload(temp_buf);
// pending the data source on last byte
temp_buf[32] = pipe_source;
if(hal_nrf_read_reg(DYNPD)>>(int)pipe_source)
temp_buf[33] = hal_nrf_read_reg(RD_RX_PLOAD_W);
else
temp_buf[33] = hal_nrf_read_reg(RX_PW_P0+pipe_source);
// epl_uart_putstr("temp_buf[33] = ");
// epl_uart_puthex(temp_buf[33]);
// epl_uart_putstr("\r\n");
usb_send_packet(temp_buf, 34);
if((hal_nrf_read_reg(STATUS))&0x10){
hal_nrf_write_reg(FLUSH_TX, 0);
}
LED0_Toggle();
}
}
break;
case EPL_SHOW_CONFIG:
epl_uart_putstr("\r\n0. CONFIG = ");
epl_uart_puthex(hal_nrf_read_reg(CONFIG));
epl_uart_putstr("\r\n1. RF_CH = ");
epl_uart_puthex(hal_nrf_read_reg(RF_CH));
epl_uart_putstr("\r\n2. EN_AA = ");
epl_uart_puthex(hal_nrf_read_reg(EN_AA));
epl_uart_putstr("\r\n3. EN_RXADDR = ");
epl_uart_puthex(hal_nrf_read_reg(EN_RXADDR));
epl_uart_putstr("\r\n4. TX_ADDR = ");
hal_nrf_read_multibyte_reg(HAL_NRF_TX, addr_buf);
epl_uart_puthex(addr_buf[0]);
epl_uart_puthex(addr_buf[1]);
epl_uart_puthex(addr_buf[2]);
epl_uart_puthex(addr_buf[3]);
epl_uart_puthex(addr_buf[4]);
epl_uart_putstr("\r\n4. RX_ADDR_PO = ");
hal_nrf_read_multibyte_reg(HAL_NRF_PIPE0, addr_buf);
epl_uart_puthex(addr_buf[0]);
epl_uart_puthex(addr_buf[1]);
epl_uart_puthex(addr_buf[2]);
epl_uart_puthex(addr_buf[3]);
epl_uart_puthex(addr_buf[4]);
epl_uart_putstr("\r\n RX_ADDR_P1 = ");
hal_nrf_read_multibyte_reg(HAL_NRF_PIPE1, addr_buf);
epl_uart_puthex(addr_buf[0]);
epl_uart_puthex(addr_buf[1]);
epl_uart_puthex(addr_buf[2]);
epl_uart_puthex(addr_buf[3]);
epl_uart_puthex(addr_buf[4]);
epl_uart_putstr("\r\n RX_ADDR_P2 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P2));
epl_uart_putstr("\r\n RX_ADDR_P3 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P3));
epl_uart_putstr("\r\n RX_ADDR_P4 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P4));
epl_uart_putstr("\r\n RX_ADDR_P5 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_ADDR_P5));
epl_uart_putstr("\r\n5. RX_PW_P0 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P0));
epl_uart_putstr("\r\n RX_PW_P1 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P1));
epl_uart_putstr("\r\n RX_PW_P2 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P2));
epl_uart_putstr("\r\n RX_PW_P3 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P3));
epl_uart_putstr("\r\n RX_PW_P4 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P4));
epl_uart_putstr("\r\n RX_PW_P5 = ");
epl_uart_puthex(hal_nrf_read_reg(RX_PW_P5));
epl_uart_putstr("\r\n6. RF_SETUP = ");
epl_uart_puthex(hal_nrf_read_reg(RF_SETUP));
epl_uart_putstr("\r\n7. STATUS = ");
epl_uart_puthex(hal_nrf_read_reg(STATUS));
epl_uart_putstr("\r\n8 .DYNPD = ");
epl_uart_puthex(hal_nrf_read_reg(DYNPD));
epl_uart_putstr("\r\n9. FEATURE = ");
epl_uart_puthex(hal_nrf_read_reg(FEATURE));
default:
break;
}// end switch case
void hal_nrf_clear_irq_flag(hal_nrf_irq_source_t int_source)
{
hal_nrf_write_reg (STATUS, SET_BIT(int_source));
}
void hal_nrf_set_rx_payload_width(uint8_t pipe_num, uint8_t pload_width)
{
hal_nrf_write_reg (RX_PW_P0 + pipe_num, pload_width);
}