static int hdp_disable(struct hdmi_connector *hdmi_connector)
{
struct hdmi *hdmi = hdmi_connector->hdmi;
const struct hdmi_platform_config *config = hdmi->config;
struct drm_device *dev = hdmi_connector->base.dev;
int i, ret = 0;
/* Disable HPD interrupt */
hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0);
hdmi_set_mode(hdmi, false);
for (i = 0; i < config->hpd_reg_cnt; i++) {
ret = regulator_disable(hdmi->hpd_regs[i]);
if (ret) {
dev_err(dev->dev, "failed to disable hpd regulator: %s (%d)\n",
config->hpd_reg_names[i], ret);
goto fail;
}
}
for (i = 0; i < config->hpd_clk_cnt; i++)
clk_disable_unprepare(hdmi->hpd_clks[i]);
ret = gpio_config(hdmi, false);
if (ret) {
dev_err(dev->dev, "failed to unconfigure GPIOs: %d\n", ret);
goto fail;
}
return 0;
fail:
return ret;
}
static void hdp_disable(struct hdmi_connector *hdmi_connector)
{
struct hdmi *hdmi = hdmi_connector->hdmi;
const struct hdmi_platform_config *config = hdmi->config;
struct device *dev = &hdmi->pdev->dev;
int i, ret = 0;
/* Disable HPD interrupt */
hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0);
msm_hdmi_set_mode(hdmi, false);
for (i = 0; i < config->hpd_clk_cnt; i++)
clk_disable_unprepare(hdmi->hpd_clks[i]);
ret = gpio_config(hdmi, false);
if (ret)
dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret);
ret = pinctrl_pm_select_sleep_state(dev);
if (ret)
dev_warn(dev, "pinctrl state chg failed: %d\n", ret);
for (i = 0; i < config->hpd_reg_cnt; i++) {
ret = regulator_disable(hdmi->hpd_regs[i]);
if (ret)
dev_warn(dev, "failed to disable hpd regulator: %s (%d)\n",
config->hpd_reg_names[i], ret);
}
}
static int hdp_disable(struct hdmi_connector *hdmi_connector)
{
struct hdmi *hdmi = hdmi_connector->hdmi;
struct drm_device *dev = hdmi_connector->base.dev;
int ret = 0;
/* Disable HPD interrupt */
hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0);
hdmi_set_mode(hdmi, false);
if (hdmi->mpp0)
ret = regulator_disable(hdmi->mpp0);
if (!ret)
ret = regulator_disable(hdmi->mvs);
if (ret) {
dev_err(dev->dev, "failed to enable regulators: %d\n", ret);
goto fail;
}
clk_disable_unprepare(hdmi->clk);
clk_disable_unprepare(hdmi->m_pclk);
clk_disable_unprepare(hdmi->s_pclk);
ret = gpio_config(hdmi, false);
if (ret) {
dev_err(dev->dev, "failed to unconfigure GPIOs: %d\n", ret);
goto fail;
}
return 0;
fail:
return ret;
}
void bsp_hdmi_hdcp_err_check(void)
{
hdmi_write(0x10010,0x45);
hdmi_write(0x10011,0x45);
hdmi_write(0x10012,0x52);
hdmi_write(0x10013,0x54);
if( (hdmi_read(0x80c0) & 0xfe) != 0x40)
hdmi_write(0x00c1, hdmi_read(0x00c1) & 0xfe);
hdmi_write(0x10010,0x52);
hdmi_write(0x10011,0x54);
hdmi_write(0x10012,0x41);
hdmi_write(0x10013,0x57);
}
/**
* sh_hdmi_phy_config()
*/
static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
{
/* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
/* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
hdmi_write(hdmi, 0x0E, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
}
static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
unsigned int reg,
unsigned int value)
{
struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
hdmi_write(hdmi, value, reg);
return 0;
}
static void hdmi_display_off(void *arg)
{
struct sh_hdmi *hdmi = arg;
struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
pr_debug("%s(%p)\n", __func__, pdata->lcd_dev);
/* PS mode e->a */
hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
}
static void hdmi_phy_8960_powerdown(struct hdmi_phy *phy)
{
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
struct hdmi *hdmi = phy_8960->hdmi;
DBG("");
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x7f);
}
/**
* sh_hdmi_configure() - Initialise HDMI for output
*/
static void sh_hdmi_configure(struct sh_hdmi *hdmi)
{
/* Configure video format */
sh_hdmi_video_config(hdmi);
/* Configure audio format */
sh_hdmi_audio_config(hdmi);
/* Configure PHY */
sh_hdmi_phy_config(hdmi);
/* Auxiliary Video Information (AVI) InfoFrame */
sh_hdmi_avi_infoframe_setup(hdmi);
/* Audio InfoFrame */
sh_hdmi_audio_infoframe_setup(hdmi);
/* Gamut Metadata packet */
sh_hdmi_gamut_metadata_setup(hdmi);
/* Audio Content Protection (ACP) Packet */
sh_hdmi_acp_setup(hdmi);
/* ISRC1 Packet */
sh_hdmi_isrc1_setup(hdmi);
/* ISRC2 Packet */
sh_hdmi_isrc2_setup(hdmi);
/*
* Control packet auto send with VSYNC control: auto send
* General control, Gamut metadata, ISRC, and ACP packets
*/
hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
msleep(10);
/* PS mode b->d, reset PLLA and PLLB */
hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
udelay(10);
hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
}
/**
* sh_hdmi_gamut_metadata_setup() - Gamut Metadata Packet of CONTROL PACKET
*/
static void sh_hdmi_gamut_metadata_setup(struct sh_hdmi *hdmi)
{
int i;
/* Gamut Metadata Packet */
hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_INDEX);
/* Packet Type = 0x0A */
hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
/* Gamut Packet is not used, so default value */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
/* Gamut Packet is not used, so default value */
hdmi_write(hdmi, 0x10, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
/* GBD bytes 0 through 27 */
for (i = 0; i <= 27; i++)
/* HDMI_CTRL_PKT_BUF_ACCESS_PB0_63H - PB27_7EH */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
}
static void hdmi_pll_disable(struct clk_hw *hw)
{
struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
struct hdmi *hdmi = phy_8960->hdmi;
unsigned int val;
DBG("");
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B);
val |= HDMI_8960_PHY_REG12_SW_RESET;
val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
/* Make sure HDMI PHY/PLL are powered down */
mb();
}
/**
* sh_hdmi_acp_setup() - Audio Content Protection Packet (ACP)
*/
static void sh_hdmi_acp_setup(struct sh_hdmi *hdmi)
{
int i;
/* Audio Content Protection Packet (ACP) */
hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_INDEX);
/* Packet Type = 0x04 */
hdmi_write(hdmi, 0x04, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
/* ACP_Type */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
/* Reserved (0) */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
/* GBD bytes 0 through 27 */
for (i = 0; i <= 27; i++)
/* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
}
static void hdmi_phy_8x74_reset(struct hdmi_phy *phy)
{
struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
struct hdmi *hdmi = phy_8x74->hdmi;
unsigned int val;
/* NOTE that HDMI_PHY_CTL is in core mmio, not phy mmio: */
val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET);
} else {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET);
}
if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
} else {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET_PLL);
}
msleep(100);
if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET);
} else {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET);
}
if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET_PLL);
} else {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
}
}
static int
hdmi_ddc_enable(void)
{
int r;
/* Soft Reset DDC Bus */
r = hdmi_set(HDMI_CTRL_PAGE, HDMI_CTRL_RESET_REG,
HDMI_CTRL_RESET_DDC_MASK);
if (r != OK) {
return r;
}
micro_delay(100000);
r = hdmi_clear(HDMI_CTRL_PAGE, HDMI_CTRL_RESET_REG,
HDMI_CTRL_RESET_DDC_MASK);
if (r != OK) {
return r;
}
micro_delay(100000);
/* Enable DDC */
r = hdmi_write(HDMI_CTRL_PAGE, HDMI_CTRL_DDC_CTRL_REG,
HDMI_CTRL_DDC_EN_MASK);
if (r != OK) {
return r;
}
/* Setup the clock (I think) */
r = hdmi_write(HDMI_CTRL_PAGE, HDMI_CTRL_DDC_CLK_REG,
HDMI_CTRL_DDC_CLK_EN_MASK);
if (r != OK) {
return r;
}
r = hdmi_write(HDMI_HDCP_OTP_PAGE, HDMI_HDCP_OTP_DDC_CLK_REG,
HDMI_HDCP_OTP_DDC_CLK_MASK);
if (r != OK) {
return r;
}
log_debug(&log, "DDC Enabled\n");
return OK;
}
/**
* sh_hdmi_isrc2_setup() - ISRC2 Packet
*/
static void sh_hdmi_isrc2_setup(struct sh_hdmi *hdmi)
{
int i;
/* ISRC2 Packet */
hdmi_write(hdmi, 0x03, HDMI_CTRL_PKT_BUF_INDEX);
/* HB0 Packet Type = 0x06 */
hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
/* Reserved (0) */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
/* Reserved (0) */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
/* PB0 UPC_EAN_ISRC_16-31 */
/* Bytes PB16-PB27 shall be set to a value of 0. */
for (i = 0; i <= 27; i++)
/* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
}
/**
* sh_hdmi_isrc1_setup() - ISRC1 Packet
*/
static void sh_hdmi_isrc1_setup(struct sh_hdmi *hdmi)
{
int i;
/* ISRC1 Packet */
hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_INDEX);
/* Packet Type = 0x05 */
hdmi_write(hdmi, 0x05, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
/* ISRC_Cont, ISRC_Valid, Reserved (0), ISRC_Status */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
/* Reserved (0) */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
/* PB0 UPC_EAN_ISRC_0-15 */
/* Bytes PB16-PB27 shall be set to a value of 0. */
for (i = 0; i <= 27; i++)
/* HDMI_CTRL_PKT_BUF_ACCESS_PB0 - PB27 */
hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0 + i);
}
void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
{
uint32_t ctrl = 0;
if (power_on) {
ctrl |= HDMI_CTRL_ENABLE;
if (!hdmi->hdmi_mode) {
ctrl |= HDMI_CTRL_HDMI;
hdmi_write(hdmi, REG_HDMI_CTRL, ctrl);
ctrl &= ~HDMI_CTRL_HDMI;
} else {
ctrl |= HDMI_CTRL_HDMI;
}
} else {
ctrl = HDMI_CTRL_HDMI;
}
hdmi_write(hdmi, REG_HDMI_CTRL, ctrl);
DBG("HDMI Core: %s, HDMI_CTRL=0x%08x",
power_on ? "Enable" : "Disable", ctrl);
}
static void hdmi_phy_8960_reset(struct hdmi_phy *phy)
{
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
struct hdmi *hdmi = phy_8960->hdmi;
unsigned int val;
val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET);
} else {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET);
}
if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
} else {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET_PLL);
}
msleep(100);
if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET);
} else {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET);
}
if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET_PLL);
} else {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
}
}
static void msm_hdmi_phy_reset(struct hdmi *hdmi)
{
unsigned int val;
val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET);
} else {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET);
}
if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
} else {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET_PLL);
}
msleep(100);
if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET);
} else {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET);
}
if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
/* pull high */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val | HDMI_PHY_CTRL_SW_RESET_PLL);
} else {
/* pull low */
hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
}
}
/**
* Stop hdmi phy macro cell tx3g4c28
*
* @hdmi: pointer on the hdmi internal structure
*/
static void sti_hdmi_tx3g4c28phy_stop(struct sti_hdmi *hdmi)
{
int val = 0;
DRM_DEBUG_DRIVER("\n");
hdmi->event_received = false;
val = HDMI_SRZ_CFG_EN_SINK_TERM_DETECTION;
val |= HDMI_SRZ_CFG_EN_BIASRES_DETECTION;
hdmi_write(hdmi, val, HDMI_SRZ_CFG);
hdmi_write(hdmi, 0, HDMI_SRZ_PLL_CFG);
/* wait PLL interrupt */
wait_event_interruptible_timeout(hdmi->wait_event,
hdmi->event_received == true,
msecs_to_jiffies
(HDMI_TIMEOUT_PLL_LOCK));
if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)
DRM_ERROR("hdmi phy pll not well disabled\n");
}
static int hdmi_connector_get_modes(struct drm_connector *connector)
{
struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector);
struct hdmi *hdmi = hdmi_connector->hdmi;
struct edid *edid;
uint32_t hdmi_ctrl;
int ret = 0;
hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL);
hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE);
edid = drm_get_edid(connector, hdmi->i2c);
hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl);
drm_mode_connector_update_edid_property(connector, edid);
if (edid) {
ret = drm_add_edid_modes(connector, edid);
kfree(edid);
}
return ret;
}
void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on)
{
uint32_t ctrl = 0;
unsigned long flags;
spin_lock_irqsave(&hdmi->reg_lock, flags);
if (power_on) {
ctrl |= HDMI_CTRL_ENABLE;
if (!hdmi->hdmi_mode) {
ctrl |= HDMI_CTRL_HDMI;
hdmi_write(hdmi, REG_HDMI_CTRL, ctrl);
ctrl &= ~HDMI_CTRL_HDMI;
} else {
ctrl |= HDMI_CTRL_HDMI;
}
} else {
ctrl = HDMI_CTRL_HDMI;
}
hdmi_write(hdmi, REG_HDMI_CTRL, ctrl);
spin_unlock_irqrestore(&hdmi->reg_lock, flags);
DBG("HDMI Core: %s, HDMI_CTRL=0x%08x",
power_on ? "Enable" : "Disable", ctrl);
}
/**
* sh_hdmi_video_config()
*/
static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
{
/*
* [7:4]: Audio sampling frequency: 48kHz
* [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
* [0]: Internal/External DE select: internal
*/
hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
/*
* [7:6]: Video output format: RGB 4:4:4
* [5:4]: Input video data width: 8 bit
* [3:1]: EAV/SAV location: channel 1
* [0]: Video input color space: RGB
*/
hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
/*
* [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
* left at 0 by default, this configures 24bpp and sets the Color Depth
* (CD) field in the General Control Packet
*/
hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
}
static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
struct hdmi *hdmi = phy_8960->hdmi;
const struct pll_rate *pll_rate = find_rate(rate);
int i;
DBG("rate=%lu", rate);
for (i = 0; pll_rate->conf[i].reg; i++)
hdmi_write(hdmi, pll_rate->conf[i].reg, pll_rate->conf[i].val);
phy_8960->pixclk = rate;
return 0;
}
unsigned int bsp_hdmi_get_hpd()
{
unsigned int ret = 0;
hdmi_write(0x10010,0x45);
hdmi_write(0x10011,0x45);
hdmi_write(0x10012,0x52);
hdmi_write(0x10013,0x54);
if(hdmi_readl(0x10038)&0x80000)
ret = 1;
else
ret = 0;
hdmi_write(0x10010,0x52);
hdmi_write(0x10011,0x54);
hdmi_write(0x10012,0x41);
hdmi_write(0x10013,0x57);
return ret;
}
unsigned int bsp_hdmi_get_hpd()
{
unsigned int ret = 0;
hdmi_write(0x10010,0x45);
hdmi_write(0x10011,0x45);
hdmi_write(0x10012,0x52);
hdmi_write(0x10013,0x54);
if( (hdmi_read(0x0243) & 0x2) == 0x2)
ret = 1;
else
ret = 0;
hdmi_write(0x10010,0x52);
hdmi_write(0x10011,0x54);
hdmi_write(0x10012,0x41);
hdmi_write(0x10013,0x57);
return ret;
}
static int
hdmi_clear(uint8_t page, uint8_t reg, uint8_t mask)
{
int r;
uint8_t val;
val = 0x00;
r = hdmi_read(page, reg, &val);
if (r != OK) {
return r;
}
val &= ~mask;
r = hdmi_write(page, reg, val);
if (r != OK) {
return r;
}
return OK;
}
void bsp_hdmi_hrst()
{
hdmi_write(0x00C1, 0x04);
}
void bsp_hdmi_standby()
{
hdmi_write(0x10020,0x07);
hdmi_write(0x1002c,0x00);
}
int bsp_hdmi_ddc_read(char cmd,char pointer,char offset,int nbyte,char * pbuf)
{
unsigned char off = offset;
unsigned int to_cnt;
int ret = 0;
hdmi_write(0x8EE3, 0x05);
hdmi_write(0x0EE3, 0x08);
to_cnt = 10;
while(nbyte > 0)
{
to_cnt = 10;
hdmi_write(0x0EE0, 0xa0 >> 1);
hdmi_write(0x0EE1, off);
hdmi_write(0x4EE0, 0x60 >> 1);
hdmi_write(0xCEE0, pointer);
hdmi_write(0x0EE2, 0x02);
hdmi_write(0x10010,0x45);
hdmi_write(0x10011,0x45);
hdmi_write(0x10012,0x52);
hdmi_write(0x10013,0x54);
while(1)
{
to_cnt--; //wait for 10ms for timeout
if(to_cnt == 0)
break;
if( (hdmi_read(0x0013) & 0x02) == 0x02)
{
hdmi_write(0x0013, hdmi_read(0x0013) & 0x02);
* pbuf++ = hdmi_read(0x8EE1);
break;
}
else if( (hdmi_read(0x0013) & 0x01) == 0x01)
{
hdmi_write(0x0013, hdmi_read(0x0013) & 0x01);
ret = -1;
break;
}
hdmi_udelay(1000);
}
nbyte --;
off ++;
}
hdmi_write(0x10010,0x52);
hdmi_write(0x10011,0x54);
hdmi_write(0x10012,0x41);
hdmi_write(0x10013,0x57);
return ret;
}
