int hme_pci_attach(device_t dev) { struct hme_pci_softc *hsc; struct hme_softc *sc; bus_space_tag_t memt; bus_space_handle_t memh; int i, error = 0; #if !(defined(__powerpc__) || defined(__sparc64__)) device_t *children, ebus_dev; struct resource *ebus_rres; int j, slot; #endif pci_enable_busmaster(dev); /* * Some Sun HMEs do have their intpin register bogusly set to 0, * although it should be 1. Correct that. */ if (pci_get_intpin(dev) == 0) pci_set_intpin(dev, 1); hsc = device_get_softc(dev); sc = &hsc->hsc_hme; sc->sc_dev = dev; sc->sc_flags |= HME_PCI; mtx_init(&sc->sc_lock, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); /* * Map five register banks: * * bank 0: HME SEB registers: +0x0000 * bank 1: HME ETX registers: +0x2000 * bank 2: HME ERX registers: +0x4000 * bank 3: HME MAC registers: +0x6000 * bank 4: HME MIF registers: +0x7000 * */ i = PCIR_BAR(0); hsc->hsc_sres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, RF_ACTIVE); if (hsc->hsc_sres == NULL) { device_printf(dev, "could not map device registers\n"); error = ENXIO; goto fail_mtx; } i = 0; hsc->hsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, RF_SHAREABLE | RF_ACTIVE); if (hsc->hsc_ires == NULL) { device_printf(dev, "could not allocate interrupt\n"); error = ENXIO; goto fail_sres; } memt = rman_get_bustag(hsc->hsc_sres); memh = rman_get_bushandle(hsc->hsc_sres); sc->sc_sebt = sc->sc_etxt = sc->sc_erxt = sc->sc_mact = sc->sc_mift = memt; bus_space_subregion(memt, memh, 0x0000, 0x1000, &sc->sc_sebh); bus_space_subregion(memt, memh, 0x2000, 0x1000, &sc->sc_etxh); bus_space_subregion(memt, memh, 0x4000, 0x1000, &sc->sc_erxh); bus_space_subregion(memt, memh, 0x6000, 0x1000, &sc->sc_mach); bus_space_subregion(memt, memh, 0x7000, 0x1000, &sc->sc_mifh); #if defined(__powerpc__) || defined(__sparc64__) OF_getetheraddr(dev, sc->sc_enaddr); #else /* * Dig out VPD (vital product data) and read NA (network address). * * The PCI HME is a PCIO chip, which is composed of two functions: * function 0: PCI-EBus2 bridge, and * function 1: HappyMeal Ethernet controller. * * The VPD of HME resides in the Boot PROM (PCI FCode) attached * to the EBus bridge and can't be accessed via the PCI capability * pointer. * ``Writing FCode 3.x Programs'' (newer ones, dated 1997 and later) * chapter 2 describes the data structure. * * We don't have a MI EBus driver since no EBus device exists * (besides the FCode PROM) on add-on HME boards. The ``no driver * attached'' message for function 0 therefore is what is expected. */ #define PCI_ROMHDR_SIZE 0x1c #define PCI_ROMHDR_SIG 0x00 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ #define PCI_ROMHDR_PTR_DATA 0x18 #define PCI_ROM_SIZE 0x18 #define PCI_ROM_SIG 0x00 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ /* reversed */ #define PCI_ROM_VENDOR 0x04 #define PCI_ROM_DEVICE 0x06 #define PCI_ROM_PTR_VPD 0x08 #define PCI_VPDRES_BYTE0 0x00 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ #define PCI_VPDRES_LARGE_LEN_LSB 0x01 #define PCI_VPDRES_LARGE_LEN_MSB 0x02 #define PCI_VPDRES_LARGE_DATA 0x03 #define PCI_VPD_SIZE 0x03 #define PCI_VPD_KEY0 0x00 #define PCI_VPD_KEY1 0x01 #define PCI_VPD_LEN 0x02 #define PCI_VPD_DATA 0x03 #define HME_ROM_READ_N(n, offs) bus_space_read_ ## n (memt, memh, (offs)) #define HME_ROM_READ_1(offs) HME_ROM_READ_N(1, (offs)) #define HME_ROM_READ_2(offs) HME_ROM_READ_N(2, (offs)) #define HME_ROM_READ_4(offs) HME_ROM_READ_N(4, (offs)) /* Search accompanying EBus bridge. */ slot = pci_get_slot(dev); if (device_get_children(device_get_parent(dev), &children, &i) != 0) { device_printf(dev, "could not get children\n"); error = ENXIO; goto fail_sres; } ebus_dev = NULL; for (j = 0; j < i; j++) { if (pci_get_class(children[j]) == PCIC_BRIDGE && pci_get_vendor(children[j]) == PCI_VENDOR_SUN && pci_get_device(children[j]) == PCI_PRODUCT_SUN_EBUS && pci_get_slot(children[j]) == slot) { ebus_dev = children[j]; break; } } if (ebus_dev == NULL) { device_printf(dev, "could not find EBus bridge\n"); error = ENXIO; goto fail_children; } /* Map EBus bridge PROM registers. */ i = PCIR_BAR(0); if ((ebus_rres = bus_alloc_resource_any(ebus_dev, SYS_RES_MEMORY, &i, RF_ACTIVE)) == NULL) { device_printf(dev, "could not map PROM registers\n"); error = ENXIO; goto fail_children; } memt = rman_get_bustag(ebus_rres); memh = rman_get_bushandle(ebus_rres); /* Read PCI Expansion ROM header. */ if (HME_ROM_READ_2(PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || (i = HME_ROM_READ_2(PCI_ROMHDR_PTR_DATA)) < PCI_ROMHDR_SIZE) { device_printf(dev, "unexpected PCI Expansion ROM header\n"); error = ENXIO; goto fail_rres; } /* Read PCI Expansion ROM data. */ if (HME_ROM_READ_4(i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || HME_ROM_READ_2(i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || HME_ROM_READ_2(i + PCI_ROM_DEVICE) != pci_get_device(dev) || (j = HME_ROM_READ_2(i + PCI_ROM_PTR_VPD)) < i + PCI_ROM_SIZE) { device_printf(dev, "unexpected PCI Expansion ROM data\n"); error = ENXIO; goto fail_rres; } /* * Read PCI VPD. * SUNW,hme cards have a single large resource VPD-R tag * containing one NA. SUNW,qfe cards have four large resource * VPD-R tags containing one NA each (all four HME chips share * the same PROM). * The VPD used on both cards is not in PCI 2.2 standard format * however. The length in the resource header is in big endian * and the end tag is non-standard (0x79) and followed by an * all-zero "checksum" byte. Sun calls this a "Fresh Choice * Ethernet" VPD... */ /* Look at the end tag to determine whether this is a VPD with 4 NAs. */ if (HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE + ETHER_ADDR_LEN) != 0x79 && HME_ROM_READ_1(j + 4 * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE + ETHER_ADDR_LEN)) == 0x79) /* Use the Nth NA for the Nth HME on this SUNW,qfe. */ j += slot * (PCI_VPDRES_LARGE_DATA + PCI_VPD_SIZE + ETHER_ADDR_LEN); if (PCI_VPDRES_ISLARGE(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) == 0 || PCI_VPDRES_LARGE_NAME(HME_ROM_READ_1(j + PCI_VPDRES_BYTE0)) != PCI_VPDRES_TYPE_VPD || (HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_LSB) << 8 | HME_ROM_READ_1(j + PCI_VPDRES_LARGE_LEN_MSB)) != PCI_VPD_SIZE + ETHER_ADDR_LEN || HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY0) != 0x4e /* N */ || HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_KEY1) != 0x41 /* A */ || HME_ROM_READ_1(j + PCI_VPDRES_LARGE_DATA + PCI_VPD_LEN) != ETHER_ADDR_LEN) { device_printf(dev, "unexpected PCI VPD\n"); error = ENXIO; goto fail_rres; } bus_space_read_region_1(memt, memh, j + PCI_VPDRES_LARGE_DATA + PCI_VPD_DATA, sc->sc_enaddr, ETHER_ADDR_LEN); fail_rres: bus_release_resource(ebus_dev, SYS_RES_MEMORY, rman_get_rid(ebus_rres), ebus_rres); fail_children: free(children, M_TEMP); if (error != 0) goto fail_sres; #endif sc->sc_burst = 64; /* XXX */ /* * call the main configure */ if ((error = hme_config(sc)) != 0) { device_printf(dev, "could not be configured\n"); goto fail_ires; } if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET | INTR_MPSAFE, NULL, hme_intr, sc, &hsc->hsc_ih)) != 0) { device_printf(dev, "couldn't establish interrupt\n"); hme_detach(sc); goto fail_ires; } return (0); fail_ires: bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(hsc->hsc_ires), hsc->hsc_ires); fail_sres: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(hsc->hsc_sres), hsc->hsc_sres); fail_mtx: mtx_destroy(&sc->sc_lock); return (error); }
static int hme_sbus_attach(device_t dev) { struct hme_sbus_softc *hsc; struct hme_softc *sc; u_long start, count; uint32_t burst; int i, error = 0; hsc = device_get_softc(dev); sc = &hsc->hsc_hme; mtx_init(&sc->sc_lock, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); /* * Map five register banks: * * bank 0: HME SEB registers * bank 1: HME ETX registers * bank 2: HME ERX registers * bank 3: HME MAC registers * bank 4: HME MIF registers * */ i = 0; hsc->hsc_seb_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, RF_ACTIVE); if (hsc->hsc_seb_res == NULL) { device_printf(dev, "cannot map SEB registers\n"); error = ENXIO; goto fail_mtx_res; } sc->sc_sebt = rman_get_bustag(hsc->hsc_seb_res); sc->sc_sebh = rman_get_bushandle(hsc->hsc_seb_res); i = 1; hsc->hsc_etx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, RF_ACTIVE); if (hsc->hsc_etx_res == NULL) { device_printf(dev, "cannot map ETX registers\n"); error = ENXIO; goto fail_seb_res; } sc->sc_etxt = rman_get_bustag(hsc->hsc_etx_res); sc->sc_etxh = rman_get_bushandle(hsc->hsc_etx_res); i = 2; hsc->hsc_erx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, RF_ACTIVE); if (hsc->hsc_erx_res == NULL) { device_printf(dev, "cannot map ERX registers\n"); error = ENXIO; goto fail_etx_res; } sc->sc_erxt = rman_get_bustag(hsc->hsc_erx_res); sc->sc_erxh = rman_get_bushandle(hsc->hsc_erx_res); i = 3; hsc->hsc_mac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, RF_ACTIVE); if (hsc->hsc_mac_res == NULL) { device_printf(dev, "cannot map MAC registers\n"); error = ENXIO; goto fail_erx_res; } sc->sc_mact = rman_get_bustag(hsc->hsc_mac_res); sc->sc_mach = rman_get_bushandle(hsc->hsc_mac_res); /* * At least on some HMEs, the MIF registers seem to be inside the MAC * range, so try to kludge around it. */ i = 4; hsc->hsc_mif_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, RF_ACTIVE); if (hsc->hsc_mif_res == NULL) { if (bus_get_resource(dev, SYS_RES_MEMORY, i, &start, &count) != 0) { device_printf(dev, "cannot get MIF registers\n"); error = ENXIO; goto fail_mac_res; } if (start < rman_get_start(hsc->hsc_mac_res) || start + count - 1 > rman_get_end(hsc->hsc_mac_res)) { device_printf(dev, "cannot move MIF registers to MAC " "bank\n"); error = ENXIO; goto fail_mac_res; } sc->sc_mift = sc->sc_mact; bus_space_subregion(sc->sc_mact, sc->sc_mach, start - rman_get_start(hsc->hsc_mac_res), count, &sc->sc_mifh); } else { sc->sc_mift = rman_get_bustag(hsc->hsc_mif_res); sc->sc_mifh = rman_get_bushandle(hsc->hsc_mif_res); } i = 0; hsc->hsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i, RF_SHAREABLE | RF_ACTIVE); if (hsc->hsc_ires == NULL) { device_printf(dev, "could not allocate interrupt\n"); error = ENXIO; goto fail_mif_res; } OF_getetheraddr(dev, sc->sc_enaddr); burst = sbus_get_burstsz(dev); /* Translate into plain numerical format */ if ((burst & SBUS_BURST_64)) sc->sc_burst = 64; else if ((burst & SBUS_BURST_32)) sc->sc_burst = 32; else if ((burst & SBUS_BURST_16)) sc->sc_burst = 16; else sc->sc_burst = 0; sc->sc_dev = dev; sc->sc_flags = 0; if ((error = hme_config(sc)) != 0) { device_printf(dev, "could not be configured\n"); goto fail_ires; } if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET | INTR_MPSAFE, NULL, hme_intr, sc, &hsc->hsc_ih)) != 0) { device_printf(dev, "couldn't establish interrupt\n"); hme_detach(sc); goto fail_ires; } return (0); fail_ires: bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(hsc->hsc_ires), hsc->hsc_ires); fail_mif_res: if (hsc->hsc_mif_res != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(hsc->hsc_mif_res), hsc->hsc_mif_res); } fail_mac_res: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(hsc->hsc_mac_res), hsc->hsc_mac_res); fail_erx_res: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(hsc->hsc_erx_res), hsc->hsc_erx_res); fail_etx_res: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(hsc->hsc_etx_res), hsc->hsc_etx_res); fail_seb_res: bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(hsc->hsc_seb_res), hsc->hsc_seb_res); fail_mtx_res: mtx_destroy(&sc->sc_lock); return (error); }
static int hme_sbus_attach(device_t dev) { struct hme_sbus_softc *hsc = device_get_softc(dev); struct hme_softc *sc = &hsc->hsc_hme; u_int32_t burst; u_long start, count; int error; /* * Map five register banks: * * bank 0: HME SEB registers * bank 1: HME ETX registers * bank 2: HME ERX registers * bank 3: HME MAC registers * bank 4: HME MIF registers * */ sc->sc_sebo = sc->sc_etxo = sc->sc_erxo = sc->sc_maco = sc->sc_mifo = 0; hsc->hsc_seb_rid = 0; hsc->hsc_seb_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &hsc->hsc_seb_rid, 0, ~0, 1, RF_ACTIVE); if (hsc->hsc_seb_res == NULL) { device_printf(dev, "cannot map SEB registers\n"); return (ENXIO); } sc->sc_sebt = rman_get_bustag(hsc->hsc_seb_res); sc->sc_sebh = rman_get_bushandle(hsc->hsc_seb_res); hsc->hsc_etx_rid = 1; hsc->hsc_etx_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &hsc->hsc_etx_rid, 0, ~0, 1, RF_ACTIVE); if (hsc->hsc_etx_res == NULL) { device_printf(dev, "cannot map ETX registers\n"); goto fail_seb_res; } sc->sc_etxt = rman_get_bustag(hsc->hsc_etx_res); sc->sc_etxh = rman_get_bushandle(hsc->hsc_etx_res); hsc->hsc_erx_rid = 2; hsc->hsc_erx_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &hsc->hsc_erx_rid, 0, ~0, 1, RF_ACTIVE); if (hsc->hsc_erx_res == NULL) { device_printf(dev, "cannot map ERX registers\n"); goto fail_etx_res; } sc->sc_erxt = rman_get_bustag(hsc->hsc_erx_res); sc->sc_erxh = rman_get_bushandle(hsc->hsc_erx_res); hsc->hsc_mac_rid = 3; hsc->hsc_mac_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &hsc->hsc_mac_rid, 0, ~0, 1, RF_ACTIVE); if (hsc->hsc_mac_res == NULL) { device_printf(dev, "cannot map MAC registers\n"); goto fail_erx_res; } sc->sc_mact = rman_get_bustag(hsc->hsc_mac_res); sc->sc_mach = rman_get_bushandle(hsc->hsc_mac_res); /* * At least on some HMEs, the MIF registers seem to be inside the MAC * range, so map try to kluge around it. */ hsc->hsc_mif_rid = 4; hsc->hsc_mif_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &hsc->hsc_mif_rid, 0, ~0, 1, RF_ACTIVE); if (hsc->hsc_mif_res == NULL) { if (bus_get_resource(dev, SYS_RES_MEMORY, hsc->hsc_mif_rid, &start, &count) != 0) { device_printf(dev, "cannot get MIF registers\n"); goto fail_mac_res; } if (start < rman_get_start(hsc->hsc_mac_res) || start + count - 1 > rman_get_end(hsc->hsc_mac_res)) { device_printf(dev, "cannot move MIF registers to MAC " "bank\n"); goto fail_mac_res; } sc->sc_mift = sc->sc_mact; sc->sc_mifh = sc->sc_mach; sc->sc_mifo = sc->sc_maco + start - rman_get_start(hsc->hsc_mac_res); } else { sc->sc_mift = rman_get_bustag(hsc->hsc_mif_res); sc->sc_mifh = rman_get_bushandle(hsc->hsc_mif_res); } hsc->hsc_irid = 0; hsc->hsc_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &hsc->hsc_irid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); if (hsc->hsc_ires == NULL) { device_printf(dev, "could not allocate interrupt\n"); error = ENXIO; goto fail_mif_res; } OF_getetheraddr(dev, sc->sc_arpcom.ac_enaddr); burst = sbus_get_burstsz(dev); /* Translate into plain numerical format */ sc->sc_burst = (burst & SBUS_BURST_32) ? 32 : (burst & SBUS_BURST_16) ? 16 : 0; sc->sc_pci = 0; /* XXX: should all be done in bus_dma. */ sc->sc_dev = dev; if ((error = hme_config(sc)) != 0) { device_printf(dev, "could not be configured\n"); goto fail_ires; } if ((error = bus_setup_intr(dev, hsc->hsc_ires, INTR_TYPE_NET, hme_intr, sc, &hsc->hsc_ih)) != 0) { device_printf(dev, "couldn't establish interrupt\n"); goto fail_ires; } return (0); fail_ires: bus_release_resource(dev, SYS_RES_IRQ, hsc->hsc_irid, hsc->hsc_ires); fail_mif_res: if (hsc->hsc_mif_res != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, hsc->hsc_mif_rid, hsc->hsc_mif_res); } fail_mac_res: bus_release_resource(dev, SYS_RES_MEMORY, hsc->hsc_mac_rid, hsc->hsc_mac_res); fail_erx_res: bus_release_resource(dev, SYS_RES_MEMORY, hsc->hsc_erx_rid, hsc->hsc_erx_res); fail_etx_res: bus_release_resource(dev, SYS_RES_MEMORY, hsc->hsc_etx_rid, hsc->hsc_etx_res); fail_seb_res: bus_release_resource(dev, SYS_RES_MEMORY, hsc->hsc_seb_rid, hsc->hsc_seb_res); return (ENXIO); }