static void ClkSet(sys_clk_t clock)
{
switch (clock)
{
case sysclk_XTAL16M:
if (!hw_cpm_check_xtal16m_status()) // XTAL16M disabled
{
hw_cpm_enable_xtal16m(); // Enable XTAL16M
}
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M); // Set XTAL16 as sys_clk
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
hw_qspi_set_div(HW_QSPI_DIV_1);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
break;
case sysclk_PLL48:
if (hw_cpm_is_pll_locked() == 0)
{
hw_watchdog_unfreeze(); // Start watchdog
hw_cpm_pll_sys_on(); // Turn on PLL
hw_watchdog_freeze(); // Stop watchdog
}
hw_cpm_enable_pll_divider(); // Enable divider (div by 2)
hw_qspi_set_div(HW_QSPI_DIV_1);
hw_cpm_set_sysclk(SYS_CLK_IS_PLL);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
break;
case sysclk_PLL96:
if (hw_cpm_is_pll_locked() == 0)
{
hw_watchdog_unfreeze(); // Start watchdog
hw_cpm_pll_sys_on(); // Turn on PLL
hw_watchdog_freeze(); // Stop watchdog
}
hw_cpm_disable_pll_divider(); // Disable divider (div by 1)
hw_qspi_set_div(HW_QSPI_DIV_2);
hw_cpm_set_sysclk(SYS_CLK_IS_PLL);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
break;
default:
break;
}
}
/* carry out clock initialization sequence */
static void nortos_clk_setup(void)
{
// Setup DIVN
if (dg_configEXT_CRYSTAL_FREQ == EXT_CRYSTAL_IS_16M)
{
hw_cpm_set_divn(false); // External crystal is 16MHz
}
else
{
hw_cpm_set_divn(true); // External crystal is 32MHz
}
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
nortos_xtal16m_settled = false;
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
/* Wait for XTAL16M to settle */
while (!nortos_xtal16m_settled);
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
}
void ClkInit(void)
{
NVIC_ClearPendingIRQ(XTAL16RDY_IRQn);
NVIC_EnableIRQ(XTAL16RDY_IRQn); // Activate XTAL16 Ready IRQ
hw_cpm_set_divn(false); // External crystal is 16MHz
hw_cpm_enable_rc32k();
hw_cpm_lp_set_rc32k();
hw_cpm_set_xtal16m_settling_time(dg_configXTAL16_SETTLE_TIME_RC32K);
hw_cpm_enable_xtal16m(); // Enable XTAL16M
hw_cpm_configure_xtal32k_pins(); // Configure XTAL32K pins
hw_cpm_configure_xtal32k(); // Configure XTAL32K
hw_cpm_enable_xtal32k(); // Enable XTAL32K
hw_watchdog_unfreeze(); // Start watchdog
while (!hw_cpm_is_xtal16m_started()); // Block until XTAL16M starts
hw_watchdog_freeze(); // Stop watchdog
hw_cpm_set_recharge_period((uint16_t)dg_configSET_RECHARGE_PERIOD);
hw_cpm_set_sysclk(SYS_CLK_IS_XTAL16M);
hw_cpm_set_hclk_div(0);
hw_cpm_set_pclk_div(0);
hw_otpc_init();
hw_otpc_set_speed(HW_OTPC_SYS_CLK_FREQ_16);
}