/**
* \brief Configure hardware blocks used by the test suite.
*
*/
static void periph_init(void)
{
# if dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_A
# define UART_TX_PORT HW_GPIO_PORT_1
# define UART_TX_PIN HW_GPIO_PIN_0
# define UART_RX_PORT HW_GPIO_PORT_1
# define UART_RX_PIN HW_GPIO_PIN_5
#elif dg_configBLACK_ORCA_MB_REV == BLACK_ORCA_MB_REV_B
# define UART_TX_PORT HW_GPIO_PORT_1
# define UART_TX_PIN HW_GPIO_PIN_3
# define UART_RX_PORT HW_GPIO_PORT_2
# define UART_RX_PIN HW_GPIO_PIN_3
# else
# error "Unknown value for dg_configBLACK_ORCA_MB_REV!"
# endif
#if LOADER_UART
#if LOADER_UART == 2
hw_gpio_set_pin_function(UART_TX_PORT, UART_TX_PIN, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_UART2_TX);
hw_gpio_set_pin_function(UART_RX_PORT, UART_RX_PIN, HW_GPIO_MODE_INPUT,
HW_GPIO_FUNC_UART2_RX);
#else
hw_gpio_set_pin_function(UART_TX_PORT, UART_TX_PIN, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_UART_TX);
hw_gpio_set_pin_function(UART_RX_PORT, UART_RX_PIN, HW_GPIO_MODE_INPUT,
HW_GPIO_FUNC_UART_RX);
#endif
hw_uart_init(UART_ID, &uart_cfg);
#endif
}
/**
* \brief Initialize the peripherals domain after power-up.
*
*/
static void periph_init(void)
{
hw_gpio_set_pin_function(HW_GPIO_PORT_1, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_UART2_TX);
hw_gpio_set_pin_function(HW_GPIO_PORT_2, HW_GPIO_PIN_3, HW_GPIO_MODE_OUTPUT,
HW_GPIO_FUNC_UART2_RX);
hw_gpio_configure_pin(CFG_TRIGGER_DELETE_BOND_GPIO_PORT, CFG_TRIGGER_DELETE_BOND_GPIO_PIN,
HW_GPIO_MODE_INPUT_PULLUP, HW_GPIO_FUNC_GPIO, 1);
}
static void periph_deinit(void)
{
#if LOADER_UART
while (!hw_uart_is_tx_fifo_empty(UART_ID)) {
}
/* Configure pins used for UART as input, since UART can be used on other pins in app */
hw_gpio_set_pin_function(UART_TX_PORT, UART_TX_PIN, HW_GPIO_MODE_INPUT, HW_GPIO_FUNC_GPIO);
hw_gpio_set_pin_function(UART_RX_PORT, UART_RX_PIN, HW_GPIO_MODE_INPUT, HW_GPIO_FUNC_GPIO);
#endif
/* Timer1 is used for ticks in OS disable it for now */
hw_timer1_disable();
}
static void set_bypass(void)
{
uint16_t m = 0;
if (fem_config.tx_bypass)
{
m = RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk;
}
if (fem_config.rx_bypass)
{
m |= RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk;
}
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_RX_Msk |
RFCU_POWER_RF_PORT_EN_REG_RF_PORT3_TX_Msk, m);
if (m == 0)
{
/* No RX/TX bypass. Drive the interface line to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CPS_PORT,
dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
}
else
{
/* At least one of TX/RX needs bypass */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CPS_PORT,
dg_configFEM_SKY66112_11_CPS_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT3_DCF);
}
}
static void set_txpower(void)
{
if (!fem_config.started)
{
return;
}
/* CHL is always 0 on RX */
REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_RX);
REG_CLR_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_RX);
if (fem_config.tx_power_ble)
{
REG_SET_BIT(RFCU_POWER, RF_PORT_EN_BLE_REG, RF_PORT4_TX);
}
if (fem_config.tx_power_ftdf)
{
REG_SET_BIT(RFCU_POWER, RF_PORT_EN_FTDF_REG, RF_PORT4_TX);
}
if (fem_config.tx_power_ble || fem_config.tx_power_ftdf)
{
/* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF);
}
else
{
/* TX Power low. Stop DCF, set GPIO to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
}
}
void hw_fem_set_txpower(bool high)
{
#if defined(dg_configFEM_SKY66112_11_CHL_PORT) && defined(dg_configFEM_SKY66112_11_CHL_PIN)
GLOBAL_INT_DISABLE();
fem_config.tx_power = high;
if (fem_config.started)
{
if (high == false)
{
/* TX Power low. Stop DCF, set GPIO to low */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, false);
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk |
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk, 0);
}
else
{
/* TX Power high. Configure GPIO for DCF. Enable DCF on TX. */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CHL_PORT,
dg_configFEM_SKY66112_11_CHL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT4_DCF);
REG_SET_MASKED(RFCU_POWER, RF_PORT_EN_REG,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_RX_Msk |
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk,
RFCU_POWER_RF_PORT_EN_REG_RF_PORT4_TX_Msk);
}
}
GLOBAL_INT_RESTORE();
#endif
}
void hw_fem_start(void)
{
GLOBAL_INT_DISABLE();
fem_config.started = true;
uint8_t set_delay;
uint8_t reset_delay;
uint16_t rf_port_en;
/******************************************************
* Setup GPIOs
*/
/* CSD GPIO Config */
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
# if dg_configFEM_SKY66112_11_CSD_USE_DCF == 0
/* Manually set CSD (Enable FEM) */
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, true);
# else
/* Use DCF for CSD */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CSD_PORT, dg_configFEM_SKY66112_11_CSD_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT2_DCF);
# endif
#endif
/* Timer 27 GPIO (DCF Port 0). Used for TX EN */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CTX_PORT, dg_configFEM_SKY66112_11_CTX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT0_DCF);
/* Timer 28 (DCF Port 1). Used for RX EN */
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_CRX_PORT, dg_configFEM_SKY66112_11_CRX_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_PORT1_DCF);
/* Antenna selection */
#if defined(dg_configFEM_SKY66112_11_ANTSEL_PORT) && defined(dg_configFEM_SKY66112_11_ANTSEL_PIN)
hw_gpio_configure_pin(dg_configFEM_SKY66112_11_ANTSEL_PORT, dg_configFEM_SKY66112_11_ANTSEL_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_GPIO, fem_config.antsel);
#endif
/******************************************************
* Setup RF_ANT_TRIM GPIOs
*/
/* RF_ANT_TRIM_0 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_0_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_0_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM0);
#endif
/* RF_ANT_TRIM_1 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_1_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_1_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM1);
#endif
/* RF_ANT_TRIM_2 Config */
#if defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT) && defined(dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN)
hw_gpio_set_pin_function(dg_configFEM_SKY66112_11_ANT_TRIM_2_PORT, dg_configFEM_SKY66112_11_ANT_TRIM_2_PIN,
HW_GPIO_MODE_OUTPUT, HW_GPIO_FUNC_RF_ANT_TRIM2);
#endif
/******************************************************
* Setup DCFs
*/
/* assign values to the timer registers for CTX/CRX (in usec) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_27_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, SET_OFFSET, dg_configFEM_SKY66112_11_RXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_28_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_RXRESET_DCF);
rf_port_en = 0x6; /* Start with Port 0: TX, Port 1: RX */
/* Compute set/reset delays to use for CSD, CPS, CHL DCFs: For setting delay,
* smaller of TXSET, RXSET, and for resetting delay, larger of TXSET, RXSET
*/
#if dg_configFEM_SKY66112_11_RXSET_DCF > dg_configFEM_SKY66112_11_TXSET_DCF
set_delay = dg_configFEM_SKY66112_11_TXSET_DCF;
#else
set_delay = dg_configFEM_SKY66112_11_RXSET_DCF;
#endif
#if dg_configFEM_SKY66112_11_RXRESET_DCF > dg_configFEM_SKY66112_11_TXRESET_DCF
reset_delay = dg_configFEM_SKY66112_11_RXRESET_DCF;
#else
reset_delay = dg_configFEM_SKY66112_11_TXRESET_DCF;
#endif
/* CSD DCF (if enabled) configuration */
#if defined(dg_configFEM_SKY66112_11_CSD_PORT) && defined(dg_configFEM_SKY66112_11_CSD_PIN)
# if dg_configFEM_SKY66112_11_CSD_USE_DCF != 0
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, SET_OFFSET, set_delay);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_29_REG, RESET_OFFSET, reset_delay);
/* enable DCF Signals for Port 2 (CSD) for both rx/tx */
rf_port_en |= 0x30;
# endif /* dg_configFEM_SKY66112_11_CSD_USE_DCF != 0 */
#endif
/* Set bypass (CPS) DCF timers (but don't enable yet) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, SET_OFFSET, set_delay);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_30_REG, RESET_OFFSET, reset_delay);
/* Set TX Power (CHL) DCF timers (but don't enable yet) */
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, SET_OFFSET, dg_configFEM_SKY66112_11_TXSET_DCF);
REG_SETF(RFCU_POWER, RF_CNTRL_TIMER_31_REG, RESET_OFFSET, dg_configFEM_SKY66112_11_TXRESET_DCF);
/* Enable DCFs */
#if dg_configBLACK_ORCA_IC_REV == BLACK_ORCA_IC_REV_A
RFCU_POWER->RF_PORT_EN_REG = rf_port_en;
hw_fem_set_txpower(fem_config.tx_power);
#else
RFCU_POWER->RF_PORT_EN_BLE_REG = rf_port_en;
RFCU_POWER->RF_PORT_EN_FTDF_REG = rf_port_en;
set_txpower();
#endif
set_bypass();
GLOBAL_INT_RESTORE();
}
