int
tegra_powergate_sequence_power_up(enum tegra_powergate_id id, clk_t clk,
hwreset_t rst)
{
struct tegra124_pmc_softc *sc;
int rv;
sc = tegra124_pmc_get_sc();
rv = hwreset_assert(rst);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert reset\n");
return (rv);
}
rv = clk_stop(clk);
if (rv != 0) {
device_printf(sc->dev, "Cannot stop clock\n");
goto clk_fail;
}
rv = tegra_powergate_power_on(id);
if (rv != 0) {
device_printf(sc->dev, "Cannot power on powergate\n");
goto clk_fail;
}
rv = clk_enable(clk);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable clock\n");
goto clk_fail;
}
DELAY(20);
rv = tegra_powergate_remove_clamping(id);
if (rv != 0) {
device_printf(sc->dev, "Cannot remove clamping\n");
goto fail;
}
rv = hwreset_deassert(rst);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset reset\n");
goto fail;
}
return 0;
fail:
clk_disable(clk);
clk_fail:
hwreset_assert(rst);
tegra_powergate_power_off(id);
return (rv);
}
static int
tegra_i2c_hw_init(struct tegra_i2c_softc *sc)
{
int rv, timeout;
/* Reset the core. */
rv = hwreset_assert(sc->reset);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert reset\n");
return (rv);
}
DELAY(10);
rv = hwreset_deassert(sc->reset);
if (rv != 0) {
device_printf(sc->dev, "Cannot clear reset\n");
return (rv);
}
WR4(sc, I2C_INTERRUPT_MASK_REGISTER, 0);
WR4(sc, I2C_INTERRUPT_STATUS_REGISTER, 0xFFFFFFFF);
WR4(sc, I2C_CNFG, I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
I2C_CNFG_DEBOUNCE_CNT(2));
tegra_i2c_setup_clk(sc, sc->bus_freq);
WR4(sc, I2C_FIFO_CONTROL, I2C_FIFO_CONTROL_TX_FIFO_TRIG(7) |
I2C_FIFO_CONTROL_RX_FIFO_TRIG(0));
WR4(sc, I2C_CONFIG_LOAD, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD);
for (timeout = 1000; timeout > 0; timeout--) {
if (RD4(sc, I2C_CONFIG_LOAD) == 0)
break;
DELAY(10);
}
if (timeout <= 0)
device_printf(sc->dev, "config load timeouted\n");
tegra_i2c_bus_clear(sc);
return (0);
}
static int
enable_fdt_resources(struct tegra_ahci_sc *sc)
{
int rv;
rv = regulator_enable(sc->supply_hvdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'hvdd' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_vddio);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'vddio' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'avdd' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_target_5v);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'target-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_target_12v);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'sc->target-12v' regulator\n");
return (rv);
}
/* Stop clocks */
clk_stop(sc->clk_sata);
clk_stop(sc->clk_sata_oob);
tegra_powergate_power_off(TEGRA_POWERGATE_SAX);
rv = hwreset_assert(sc->hwreset_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata oob' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot assert 'sata cold' reset\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX,
sc->clk_sata, sc->hwreset_sata);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'SAX' powergate\n");
return (rv);
}
rv = clk_enable(sc->clk_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'sata oob' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_cml);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'cml' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_pll_e);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable 'pll e' clock\n");
return (rv);
}
rv = hwreset_deassert(sc->hwreset_sata_cold);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n");
return (rv);
}
rv = hwreset_deassert(sc->hwreset_sata_oob);
if (rv != 0) {
device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n");
return (rv);
}
rv = phy_enable(sc->dev, sc->phy);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable SATA phy\n");
return (rv);
}
return (0);
}
static int
enable_fdt_resources(struct tegra_xhci_softc *sc)
{
int rv;
rv = hwreset_assert(sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_host' reset\n");
return (rv);
}
rv = hwreset_assert(sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot reset 'xusb_ss' reset\n");
return (rv);
}
rv = regulator_enable(sc->supply_avddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_dvddio_pex);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'dvddio_pex' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_utmip);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_utmip-5v' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_pll_erefe);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_pll_erefe' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_avdd_usb_ss_pll);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'avdd_usb_ss_pll' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss' regulator\n");
return (rv);
}
rv = regulator_enable(sc->supply_hvdd_usb_ss_pll_e);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'hvdd_usb_ss_pll_e' regulator\n");
return (rv);
}
/* Power off XUSB host and XUSB SS domains. */
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusba' domain\n");
return (rv);
}
rv = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerdown 'xusbc' domain\n");
return (rv);
}
/* Setup XUSB ss_src clock first */
clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0);
if (rv != 0)
return (rv);
/* The XUSB gate clock must be enabled before XUSBA can be powered. */
rv = clk_enable(sc->clk_xusb_gate);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_gate' clock\n");
return (rv);
}
/* Power on XUSB host and XUSB SS domains. */
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
sc->clk_xusb_host, sc->hwreset_xusb_host);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusbc' domain\n");
return (rv);
}
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
sc->clk_xusb_ss, sc->hwreset_xusb_ss);
if (rv != 0) {
device_printf(sc->dev, "Cannot powerup 'xusba' domain\n");
return (rv);
}
/* Enable rest of clocks */
rv = clk_enable(sc->clk_xusb_falcon_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_falcon_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_fs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_fs_src' clock\n");
return (rv);
}
rv = clk_enable(sc->clk_xusb_hs_src);
if (rv != 0) {
device_printf(sc->dev,
"Cannot enable 'xusb_hs_src' clock\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_0 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_1);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_1 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb2_2);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB2_2 phy\n");
return (rv);
}
rv = phy_enable(sc->phy_usb3_0);
if (rv != 0) {
device_printf(sc->dev, "Cannot enable USB3_0 phy\n");
return (rv);
}
return (0);
}
