/*
* Waiting on Bus Busy
*/
static int i2c_davinci_wait_for_bb(char allow_sleep, struct i2c_adapter *adap)
{
unsigned long timeout;
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
int i;
static char to_cnt = 0;
timeout = jiffies + DAVINCI_I2C_TIMEOUT;
while ((i2c_davinci_dev.regs->icstr) & DAVINCI_I2C_ICSTR_BB_MASK) {
if (to_cnt <= 2) {
if (time_after(jiffies, timeout)) {
i2c_warn("timeout waiting for bus ready");
to_cnt ++;
return -ETIMEDOUT;
}
} else if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) {
to_cnt = 0;
/* Send the NACK to the slave */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_NACKMOD_MASK;
/* Disable I2C */
disable_i2c_pins();
for (i = 0; i < 10; i++)
pulse_i2c_clock();
/* Re-enable I2C */
enable_i2c_pins();
i2c_davinci_reset(dev);
dev->cmd_complete = 0;
return -ETIMEDOUT;
}
if (allow_sleep)
schedule_timeout(1);
}
return 0;
}
static int __init i2c_davinci_init(void)
{
int status;
struct device *dev = NULL;
DEB0("%s %s", __TIME__, __DATE__);
DEB1("i2c_davinci_init()\n");
davinci_i2c_fix_ths7353_lockup( );
#if 0
if (i2c_davinci_busFreq > 200)
i2c_davinci_busFreq = 400; /*Fast mode */
else
i2c_davinci_busFreq = 100; /*Standard mode */
#endif
i2c_clock = clk_get (dev, "I2CCLK");
if (i2c_clock == NULL)
return -1;
clk_use (i2c_clock);
clk_enable (i2c_clock);
i2c_davinci_inputClock = clk_get_rate (i2c_clock);
DEB1 ("IP CLOCK = %ld\n", i2c_davinci_inputClock);
memset(&i2c_davinci_dev, 0, sizeof(i2c_davinci_dev));
i2c_davinci_dev.regs = (davinci_i2cregsovly)I2C_BASE;
status = (int)request_region(I2C_BASE, I2C_IOSIZE, MODULE_NAME);
if (!status) {
i2c_err("I2C is already in use\n");
return -ENODEV;
}
status = request_irq(IRQ_I2C, i2c_davinci_isr, 0, MODULE_NAME,
&i2c_davinci_dev);
if (status) {
i2c_err("failed to request I2C IRQ");
goto do_release_region;
}
i2c_set_adapdata(&i2c_davinci_adap, &i2c_davinci_dev);
status = i2c_add_adapter(&i2c_davinci_adap);
if (status) {
i2c_err("failed to add adapter");
goto do_free_irq;
return status;
}
i2c_davinci_reset(&i2c_davinci_dev);
if (driver_register(&davinci_i2c_driver) != 0)
printk(KERN_ERR "Driver register failed for davinci_i2c\n");
if (platform_device_register(&davinci_i2c_device) != 0) {
printk(KERN_ERR "Device register failed for i2c\n");
driver_unregister(&davinci_i2c_driver);
}
return 0;
do_free_irq:
free_irq(IRQ_I2C, &i2c_davinci_dev);
do_release_region:
release_region(I2C_BASE, I2C_IOSIZE);
return status;
}
/*
* Low level master read/write transaction. This function is called
* from i2c_davinci_xfer.
*/
static int
i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
{
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
u8 zero_byte = 0;
u32 flag = 0, stat = 0;
unsigned long flags;
int r;
int cnt = 2000;
/* Introduce a 20musec delay. Required for Davinci EVM */
while (cnt--);
DEB1("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d",
msg->addr, msg->len, msg->flags, stop);
spin_lock_irqsave( &i2c_spinlock, flags );
/* set the slave address */
dev->regs->icsar = msg->addr;
/* Sigh, seems we can't do zero length transactions. Thus, we
* can't probe for devices w/o actually sending/receiving at least
* a single byte. So we'll set count to 1 for the zero length
* transaction case and hope we don't cause grief for some
* arbitrary device due to random byte write/read during
* probes.
*/
if (msg->len == 0) {
dev->buf = &zero_byte;
dev->buf_len = 1;
} else {
dev->buf = msg->buf;
dev->buf_len = msg->len;
}
dev->regs->iccnt = dev->buf_len;
dev->cmd_err = 0;
init_completion( &dev->cmd_completion );
/* Clear any pending interrupts by reading the IVR */
stat = dev->regs->icivr;
/* Take I2C out of reset, configure it as master and set the start bit */
flag =
DAVINCI_I2C_ICMDR_IRS_MASK | DAVINCI_I2C_ICMDR_MST_MASK |
DAVINCI_I2C_ICMDR_STT_MASK;
/* if the slave address is ten bit address, enable XA bit */
if (msg->flags & I2C_M_TEN)
flag |= DAVINCI_I2C_ICMDR_XA_MASK;
if (!(msg->flags & I2C_M_RD))
flag |= DAVINCI_I2C_ICMDR_TRX_MASK;
if (stop)
flag |= DAVINCI_I2C_ICMDR_STP_MASK;
/* write the data into mode register */
dev->regs->icmdr = flag;
/* Enable receive and transmit interrupts */
if (msg->flags & I2C_M_RD)
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICRRDY_MASK;
else {
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICXRDY_MASK;
/* Prime the pump */
if ( dev->regs->icstr & DAVINCI_I2C_ICSTR_ICXRDY_MASK ) {
dev->regs->icdxr = *dev->buf++;
dev->buf_len--;
}
}
spin_unlock_irqrestore( &i2c_spinlock, flags );
/* wait for the transaction to complete */
r = wait_for_completion_interruptible_timeout( &dev->cmd_completion,
DAVINCI_I2C_TIMEOUT );
dev->buf_len = 0;
if ( r < 0 ) {
return r;
}
if (r == 0 ) {
printk( "I2C command timeout, icivr=0x%04x, status=0x%04x\n",
dev->regs->icivr, dev->regs->icstr );
i2c_davinci_reset(dev);
return -ETIMEDOUT;
}
/* no error */
if (!dev->cmd_err)
return msg->len;
/* We have an error */
if (dev->cmd_err & DAVINCI_I2C_ICSTR_NACK_MASK) {
if (msg->flags & I2C_M_IGNORE_NAK)
return msg->len;
if (stop)
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_STP_MASK;
return -EREMOTEIO;
}
if (dev->cmd_err & DAVINCI_I2C_ICSTR_AL_MASK ||
dev->cmd_err & DAVINCI_I2C_ICSTR_RSFULL_MASK) {
i2c_davinci_reset(dev);
return -EIO;
}
return msg->len;
}
static int __init i2c_davinci_init(void)
{
int status;
struct device *dev = NULL;
DEB0("%s %s", __TIME__, __DATE__);
DEB1("i2c_davinci_init()");
if (cpu_is_davinci_dm6467())
davinci_i2c_expander_op (0x3A, I2C_INT_DM646X, 0);
/*
* NOTE: On DaVinci EVM, the i2c bus frequency is set to 20kHz
* so that the MSP430, which is doing software i2c, has
* some extra processing time
*/
if (machine_is_davinci_evm())
i2c_davinci_busFreq = 20;
else if (machine_is_davinci_dm6467_evm())
i2c_davinci_busFreq = 100;
else if (i2c_davinci_busFreq > 200)
i2c_davinci_busFreq = 400; /*Fast mode */
else
i2c_davinci_busFreq = 100; /*Standard mode */
i2c_clock = clk_get (dev, "I2CCLK");
if (IS_ERR(i2c_clock))
return -1;
clk_use (i2c_clock);
clk_enable (i2c_clock);
i2c_davinci_inputClock = clk_get_rate (i2c_clock);
DEB1 ("IP CLOCK = %ld", i2c_davinci_inputClock);
memset(&i2c_davinci_dev, 0, sizeof(i2c_davinci_dev));
init_waitqueue_head(&i2c_davinci_dev.cmd_wait);
i2c_davinci_dev.regs = (davinci_i2cregsovly)I2C_BASE;
status = (int)request_region(I2C_BASE, I2C_IOSIZE, MODULE_NAME);
if (!status) {
i2c_err("I2C is already in use\n");
return -ENODEV;
}
status = request_irq(IRQ_I2C, i2c_davinci_isr, 0, "i2c",
&i2c_davinci_dev);
if (status) {
i2c_err("failed to request I2C IRQ");
goto do_release_region;
}
i2c_set_adapdata(&i2c_davinci_adap, &i2c_davinci_dev);
status = i2c_add_adapter(&i2c_davinci_adap);
if (status) {
i2c_err("failed to add adapter");
goto do_free_irq;
}
i2c_davinci_reset(&i2c_davinci_dev);
if (driver_register(&davinci_i2c_driver) != 0)
printk(KERN_ERR "Driver register failed for davinci_i2c\n");
if (platform_device_register(&davinci_i2c_device) != 0) {
printk(KERN_ERR "Device register failed for i2c\n");
driver_unregister(&davinci_i2c_driver);
}
return 0;
do_free_irq:
free_irq(IRQ_I2C, &i2c_davinci_dev);
do_release_region:
release_region(I2C_BASE, I2C_IOSIZE);
return status;
}
/*
* Low level master read/write transaction. This function is called
* from i2c_davinci_xfer.
*/
static int
i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
{
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
u8 zero_byte = 0;
u32 flag = 0, stat = 0;
int i;
DEB1("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d",
msg->addr, msg->len, msg->flags, stop);
/* Introduce a 100musec delay. Required for Davinci EVM board only */
if (cpu_is_davinci_dm644x())
udelay(100);
/* set the slave address */
dev->regs->icsar = msg->addr;
/* Sigh, seems we can't do zero length transactions. Thus, we
* can't probe for devices w/o actually sending/receiving at least
* a single byte. So we'll set count to 1 for the zero length
* transaction case and hope we don't cause grief for some
* arbitrary device due to random byte write/read during
* probes.
*/
if (msg->len == 0) {
dev->buf = &zero_byte;
dev->buf_len = 1;
} else {
dev->buf = msg->buf;
dev->buf_len = msg->len;
}
dev->regs->iccnt = dev->buf_len;
dev->cmd_complete = 0;
dev->cmd_err = 0;
/* Clear any pending interrupts by reading the IVR */
stat = dev->regs->icivr;
/* Take I2C out of reset, configure it as master and set the start bit */
flag =
DAVINCI_I2C_ICMDR_IRS_MASK | DAVINCI_I2C_ICMDR_MST_MASK |
DAVINCI_I2C_ICMDR_STT_MASK;
/* if the slave address is ten bit address, enable XA bit */
if (msg->flags & I2C_M_TEN)
flag |= DAVINCI_I2C_ICMDR_XA_MASK;
if (!(msg->flags & I2C_M_RD))
flag |= DAVINCI_I2C_ICMDR_TRX_MASK;
if (stop)
flag |= DAVINCI_I2C_ICMDR_STP_MASK;
/* Enable receive and transmit interrupts */
if (msg->flags & I2C_M_RD)
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICRRDY_MASK;
else
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICXRDY_MASK;
/* write the data into mode register */
dev->regs->icmdr = flag;
/* wait for the transaction to complete */
wait_event_timeout (dev->cmd_wait, dev->cmd_complete, DAVINCI_I2C_TIMEOUT);
dev->buf_len = 0;
if (!dev->cmd_complete) {
i2c_warn("i2c: cmd complete failed: complete = 0x%x, \
icstr = 0x%x\n", dev->cmd_complete,
dev->regs->icstr);
if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) {
/* Send the NACK to the slave */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_NACKMOD_MASK;
/* Disable I2C */
disable_i2c_pins();
/* Send high and low on the SCL line */
for (i = 0; i < 10; i++)
pulse_i2c_clock();
/* Re-enable I2C */
enable_i2c_pins();
}
i2c_davinci_reset(dev);
dev->cmd_complete = 0;
return -ETIMEDOUT;
}
dev->cmd_complete = 0;
/* no error */
if (!dev->cmd_err)
return msg->len;
/* We have an error */
if (dev->cmd_err & DAVINCI_I2C_ICSTR_NACK_MASK) {
if (msg->flags & I2C_M_IGNORE_NAK)
return msg->len;
if (stop)
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_STP_MASK;
return -EREMOTEIO;
}
if (dev->cmd_err & DAVINCI_I2C_ICSTR_AL_MASK) {
i2c_davinci_reset(dev);
return -EIO;
}
return msg->len;
}
