/**
* @brief Process an i2c transaction.
*
* Transactions are composed of one or more i2c_msg's, and may be read
* or write tranfers. Multiple i2c_msg's will generate a repeated
* start in between messages.
*
* @param dev I2C device
* @param msgs Messages to send/receive
* @param num Number of messages to send/receive
* @param timeout Bus idle timeout in milliseconds before aborting the
* transfer. 0 denotes no timeout.
* @return 0 on success,
* I2C_ERROR_PROTOCOL if there was a protocol error,
* I2C_ERROR_TIMEOUT if the transfer timed out.
*/
int32 i2c_master_xfer(i2c_dev *dev,
i2c_msg *msgs,
uint16 num,
uint32 timeout) {
int32 rc;
fooprint("master xfer1");
//fooprint("me1");
ASSERT(dev->state == I2C_STATE_IDLE);
dev->msg = msgs;
dev->msgs_left = num;
// what is this?????????????????????????????????????????
dev->timestamp = systick_uptime();
dev->state = I2C_STATE_BUSY;
// workaround repeated start issue identified in SiM3U1XX Errata
dev->regs->SCONFIG |= 1 << I2C_SCONFIG_SETUP_BIT;
// already enabled in master enable
//i2c_enable_irq(dev, I2C_IRQ_EVENT);
fooprint("master exfer2");
i2c_start_condition(dev);
fooprint("master exfer3");
rc = wait_for_state_change(dev, I2C_STATE_XFER_DONE, timeout);
fooprint("master exfer after wait for state");
if (rc < 0) {
goto out;
}
dev->state = I2C_STATE_IDLE;
out:
return rc;
}
/**
* @brief Process an i2c transaction.
*
* Transactions are composed of one or more i2c_msg's, and may be read
* or write tranfers. Multiple i2c_msg's will generate a repeated
* start in between messages.
*
* @param dev I2C device
* @param msgs Messages to send/receive
* @param num Number of messages to send/receive
* @param timeout Bus idle timeout in milliseconds before aborting the
* transfer. 0 denotes no timeout.
* @return 0 on success,
* I2C_ERROR_PROTOCOL if there was a protocol error,
* I2C_ERROR_TIMEOUT if the transfer timed out.
*/
int32 i2c_master_xfer(i2c_dev *dev,
i2c_msg *msgs,
uint16 num,
uint32 timeout) {
int32 rc;
ASSERT(dev->state == I2C_STATE_IDLE);
dev->msg = msgs;
dev->msgs_left = num;
dev->timestamp = systick_uptime();
dev->state = I2C_STATE_BUSY;
i2c_enable_irq(dev, I2C_IRQ_EVENT);
i2c_start_condition(dev);
rc = wait_for_state_change(dev, I2C_STATE_XFER_DONE, timeout);
if (rc < 0) {
goto out;
}
dev->state = I2C_STATE_IDLE;
out:
return rc;
}
void i2c_send_packet(unsigned char value, unsigned char address)
{
i2c_start_condition();
i2c_send_byte(address);
i2c_send_byte(value);
i2c_stop_condition();
}
unsigned int serial_out_i2c(unsigned int addr, int offset, int value)
{
//printk( "serial_out_i2c(%X):%X,%X\n", addr, offset, value );
unsigned short int data_hibyte;
unsigned short int data_lowbyte;
data_hibyte =(unsigned char) (value>>8);
data_lowbyte =(unsigned char) (value & 0xff);
if( addr != ALC5628_I2C_ADDR )
return 0;
//printk("(%d)", __LINE__);
// start
i2c_start_condition( &alc5628_i2c_dev );
// addr + write
i2c_serial_write_byte( &alc5628_i2c_dev, ALC5628_I2C_ADDR | ALC5628_I2C_WRITE );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
//printk("(%d)", __LINE__);
// write register address
i2c_serial_write_byte( &alc5628_i2c_dev, offset );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
//printk("(%d)", __LINE__);
// write data hibyte
i2c_serial_write_byte( &alc5628_i2c_dev, data_hibyte );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
//printk("(%d)", __LINE__);
// write data lowbyte
i2c_serial_write_byte( &alc5628_i2c_dev, data_lowbyte );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
//printk("(%d)", __LINE__);
// stop
i2c_stop_condition( &alc5628_i2c_dev );
return 0;
}
/*
* IRQ handler for I2C master. Handles transmission/reception.
*/
void _i2c_irq_handler(i2c_dev *dev) {
/* WTFs:
* - Where is I2C_MSG_10BIT_ADDR handled?
*/
i2c_msg *msg = dev->msg;
uint8 read = msg->flags & I2C_MSG_READ;
uint32 sr1 = dev->regs->SR1;
uint32 sr2 = dev->regs->SR2;
I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* Add Slave support
*/
/* Check to see if MSL master slave bit is set */
if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
/* Check for address match */
if (sr1 & I2C_SR1_ADDR) {
/* Find out which address was matched */
/* Check the general call address first */
if (sr2 & I2C_SR2_GENCALL) {
dev->i2c_slave_msg->addr = 0;
}
/* We matched the secondary address */
else if (sr2 & I2C_SR2_DUALF) {
dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE;
}
/* We matched the primary address */
else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) {
dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE;
}
/* Shouldn't get here */
else {
dev->i2c_slave_msg->addr = -1; /* uh oh */
}
/* if we have buffered io */
if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* if receiving then this would be a repeated start
*
*if we have some bytes already
*/
if ((dev->state == I2C_STATE_SL_RX) &&
(dev->i2c_slave_msg->xferred > 0) &&
(dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
/* Call the callback with the contents of the data */
if (dev->i2c_slave_recv_callback != NULL) {
(*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
}
/* Reset the message back to defaults.
* We are starting a new message
*/
dev->i2c_slave_msg->flags = 0;
dev->i2c_slave_msg->length = 0;
dev->i2c_slave_msg->xferred = 0;
dev->msgs_left = 0;
dev->timestamp = systick_uptime();
/* We have been addressed with SLA+R so
* the master wants us to transmit
*/
if ((sr1 & I2C_SR1_TXE) &&
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* Call the transmit callback so it can populate the msg
* data with the bytes to go
*/
if (dev->i2c_slave_transmit_callback != NULL) {
(*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
}
dev->state = I2C_STATE_BUSY;
}
sr1 = sr2 = 0;
}
/* EV3: Master requesting data from slave. Transmit a byte*/
if (sr1 & I2C_SR1_TXE) {
if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) {
if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) {
/* End of the transmit buffer? If so we NACK */
i2c_disable_ack(dev);
/* We have to either issue a STOP or write something here.
* STOP here seems to screw up some masters,
* For now padding with 0
*/
i2c_write(dev, 0);
/*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/
}
else
{
/* NACk the last byte */
if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) {
i2c_disable_ack(dev);
}
else {
i2c_enable_ack(dev);
}
i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]);
}
}
else
{
/* Call the callback to get the data we need.
* The callback is expected to write using i2c_write(...)
* If the slave is going to terminate the transfer, this function should
* also do a NACK on the last byte!
*/
if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_BUSY;
sr1 = sr2 = 0;
}
/* EV2: Slave received data from a master. Get from DR */
if (sr1 & I2C_SR1_RXNE) {
if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) {
/* Fill the buffer with the contents of the data register */
/* These is potential for buffer overflow here, so we should
* really store the size of the array. This is expensive in
* the ISR so left out for now. We must trust the implementor!
*/
dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR;
dev->i2c_slave_msg->length++;
}
else {
/* Call the callback with the contents of the data */
dev->i2c_slave_msg->data[0] = dev->regs->DR;
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
dev->state = I2C_STATE_SL_RX;
sr1 = sr2 = 0;
}
/* EV4: Slave has detected a STOP condition on the bus */
if (sr1 & I2C_SR1_STOPF) {
dev->regs->CR1 |= I2C_CR1_PE;
if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
/* The callback with the data will happen on a NACK of the last data byte.
* This is handled in the error IRQ (AF bit)
*/
/* Handle the case where the master misbehaves by sending no NACK */
if (dev->state != I2C_STATE_IDLE) {
if (dev->state == I2C_STATE_SL_RX) {
if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
}
else {
if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
}
}
}
sr1 = sr2 = 0;
dev->state = I2C_STATE_IDLE;
}
return;
}
/*
* EV5: Start condition sent
*/
if (sr1 & I2C_SR1_SB) {
msg->xferred = 0;
i2c_enable_irq(dev, I2C_IRQ_BUFFER);
/*
* Master receiver
*/
if (read) {
i2c_enable_ack(dev);
}
i2c_send_slave_addr(dev, msg->addr, read);
sr1 = sr2 = 0;
}
/*
* EV6: Slave address sent
*/
if (sr1 & I2C_SR1_ADDR) {
/*
* Special case event EV6_1 for master receiver.
* Generate NACK and restart/stop condition after ADDR
* is cleared.
*/
if (read) {
if (msg->length == 1) {
i2c_disable_ack(dev);
if (dev->msgs_left > 1) {
i2c_start_condition(dev);
I2C_CRUMB(RX_ADDR_START, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RX_ADDR_STOP, 0, 0);
}
}
} else {
/*
* Master transmitter: write first byte to fill shift
* register. We should get another TXE interrupt
* immediately to fill DR again.
*/
if (msg->length != 1) {
i2c_write(dev, msg->data[msg->xferred++]);
}
}
sr1 = sr2 = 0;
}
/*
* EV8: Master transmitter
* Transmit buffer empty, but we haven't finished transmitting the last
* byte written.
*/
if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_ONLY, 0, 0);
if (dev->msgs_left) {
i2c_write(dev, msg->data[msg->xferred++]);
if (msg->xferred == msg->length) {
/*
* End of this message. Turn off TXE/RXNE and wait for
* BTF to send repeated start or stop condition.
*/
i2c_disable_irq(dev, I2C_IRQ_BUFFER);
dev->msgs_left--;
}
} else {
/*
* This should be impossible...
*/
ASSERT(0);
}
sr1 = sr2 = 0;
}
/*
* EV8_2: Master transmitter
* Last byte sent, program repeated start/stop
*/
if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_BTF, 0, 0);
if (dev->msgs_left) {
I2C_CRUMB(TEST, 0, 0);
/*
* Repeated start insanity: We can't disable ITEVTEN or else SB
* won't interrupt, but if we don't disable ITEVTEN, BTF will
* continually interrupt us. What the f**k ST?
*/
i2c_start_condition(dev);
while (!(dev->regs->SR1 & I2C_SR1_SB))
;
dev->msg++;
} else {
i2c_stop_condition(dev);
/*
* Turn off event interrupts to keep BTF from firing until
* the end of the stop condition. Why on earth they didn't
* have a start/stop condition request clear BTF is beyond
* me.
*/
i2c_disable_irq(dev, I2C_IRQ_EVENT);
I2C_CRUMB(STOP_SENT, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
}
sr1 = sr2 = 0;
}
/*
* EV7: Master Receiver
*/
if (sr1 & I2C_SR1_RXNE) {
I2C_CRUMB(RXNE_ONLY, 0, 0);
msg->data[msg->xferred++] = dev->regs->DR;
/*
* EV7_1: Second to last byte in the reception? Set NACK and generate
* stop/restart condition in time for the last byte. We'll get one more
* RXNE interrupt before shutting things down.
*/
if (msg->xferred == (msg->length - 1)) {
i2c_disable_ack(dev);
if (dev->msgs_left > 2) {
i2c_start_condition(dev);
I2C_CRUMB(RXNE_START_SENT, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
}
} else if (msg->xferred == msg->length) {
dev->msgs_left--;
if (dev->msgs_left == 0) {
/*
* We're done.
*/
I2C_CRUMB(RXNE_DONE, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
} else {
dev->msg++;
}
}
}
}
/**
* @brief IRQ handler for I2C master. Handles transmission/reception.
* @param dev I2C device
*/
static void i2c_irq_handler(i2c_dev *dev) {
i2c_msg *msg = dev->msg;
uint8 read = msg->flags & I2C_MSG_READ;
uint32 sr1 = dev->regs->SR1;
uint32 sr2 = dev->regs->SR2;
I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* EV5: Start condition sent
*/
if (sr1 & I2C_SR1_SB) {
msg->xferred = 0;
i2c_enable_irq(dev, I2C_IRQ_BUFFER);
/*
* Master receiver
*/
if (read) {
i2c_enable_ack(dev);
}
i2c_send_slave_addr(dev, msg->addr, read);
sr1 = sr2 = 0;
}
/*
* EV6: Slave address sent
*/
if (sr1 & I2C_SR1_ADDR) {
/*
* Special case event EV6_1 for master receiver.
* Generate NACK and restart/stop condition after ADDR
* is cleared.
*/
if (read) {
if (msg->length == 1) {
i2c_disable_ack(dev);
if (dev->msgs_left > 1) {
i2c_start_condition(dev);
I2C_CRUMB(RX_ADDR_START, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RX_ADDR_STOP, 0, 0);
}
}
} else {
/*
* Master transmitter: write first byte to fill shift
* register. We should get another TXE interrupt
* immediately to fill DR again.
*/
if (msg->length != 1) {
i2c_write(dev, msg->data[msg->xferred++]);
}
}
sr1 = sr2 = 0;
}
/*
* EV8: Master transmitter
* Transmit buffer empty, but we haven't finished transmitting the last
* byte written.
*/
if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_ONLY, 0, 0);
if (dev->msgs_left) {
i2c_write(dev, msg->data[msg->xferred++]);
if (msg->xferred == msg->length) {
/*
* End of this message. Turn off TXE/RXNE and wait for
* BTF to send repeated start or stop condition.
*/
i2c_disable_irq(dev, I2C_IRQ_BUFFER);
dev->msgs_left--;
}
} else {
/*
* This should be impossible...
*/
throb();
}
sr1 = sr2 = 0;
}
/*
* EV8_2: Master transmitter
* Last byte sent, program repeated start/stop
*/
if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
I2C_CRUMB(TXE_BTF, 0, 0);
if (dev->msgs_left) {
I2C_CRUMB(TEST, 0, 0);
/*
* Repeated start insanity: We can't disable ITEVTEN or else SB
* won't interrupt, but if we don't disable ITEVTEN, BTF will
* continually interrupt us. What the f**k ST?
*/
i2c_start_condition(dev);
while (!(dev->regs->SR1 & I2C_SR1_SB))
;
dev->msg++;
} else {
i2c_stop_condition(dev);
/*
* Turn off event interrupts to keep BTF from firing until
* the end of the stop condition. Why on earth they didn't
* have a start/stop condition request clear BTF is beyond
* me.
*/
i2c_disable_irq(dev, I2C_IRQ_EVENT);
I2C_CRUMB(STOP_SENT, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
}
sr1 = sr2 = 0;
}
/*
* EV7: Master Receiver
*/
if (sr1 & I2C_SR1_RXNE) {
I2C_CRUMB(RXNE_ONLY, 0, 0);
msg->data[msg->xferred++] = dev->regs->DR;
/*
* EV7_1: Second to last byte in the reception? Set NACK and generate
* stop/restart condition in time for the last byte. We'll get one more
* RXNE interrupt before shutting things down.
*/
if (msg->xferred == (msg->length - 1)) {
i2c_disable_ack(dev);
if (dev->msgs_left > 2) {
i2c_start_condition(dev);
I2C_CRUMB(RXNE_START_SENT, 0, 0);
} else {
i2c_stop_condition(dev);
I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
}
} else if (msg->xferred == msg->length) {
dev->msgs_left--;
if (dev->msgs_left == 0) {
/*
* We're done.
*/
I2C_CRUMB(RXNE_DONE, 0, 0);
dev->state = I2C_STATE_XFER_DONE;
} else {
dev->msg++;
}
}
}
}
unsigned int serial_in_i2c(unsigned int addr, int offset)
{
unsigned short int data_hibyte=0;
unsigned short int data_lowbyte=0;
unsigned short int data;
//printk( "serial_in_i2c(%X):%X\n", addr, offset );
if( addr != ALC5628_I2C_ADDR )
return 0;
// start
i2c_start_condition( &alc5628_i2c_dev );
// addr + write
i2c_serial_write_byte( &alc5628_i2c_dev, ALC5628_I2C_ADDR |
ALC5628_I2C_WRITE );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
// write register address
i2c_serial_write_byte( &alc5628_i2c_dev, offset );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
// start
i2c_start_condition( &alc5628_i2c_dev );
// addr + read
i2c_serial_write_byte( &alc5628_i2c_dev, ALC5628_I2C_ADDR |
ALC5628_I2C_READ );
// read ACK
if( i2c_ACK( &alc5628_i2c_dev ) != 0 )
return 0;
// read data_hibyte
i2c_serial_read( &alc5628_i2c_dev, &data_hibyte );
//write ACK
i2c_ACK_w(&alc5628_i2c_dev, 0);
// read data_lowbyte
i2c_serial_read( &alc5628_i2c_dev, &data_lowbyte );
data = (data_hibyte<<8) | data_lowbyte;
// write negative-ACK
i2c_ACK_w( &alc5628_i2c_dev, 1 );
// stop
i2c_stop_condition( &alc5628_i2c_dev );
//printk( "in[%X]\n", data );
return data;
}
/*
@func int | _rtl865xC_i2c_rawWrite_alc5621 | Write several bits to device
@parm i2c_dev_t* | pI2C_Dev | Structure containing device information
@parm unsigned char* | pDEV_ID | i2c id address
@parm unsigned char* | pReg | i2c register address
@parm unsigned short int* | pData | i2c data
@comm
*/
static void __i2c_rawWrite_alc5621( i2c_dev_t* pI2C_Dev, const unsigned char *pDEV_ID, unsigned char *pReg, unsigned short int *pData)
{
int i;
//char j;
//unsigned int buf;
unsigned char dev_id, reg, data_hibyte, data_lowbyte;
if ((pData == NULL) || (pDEV_ID == NULL) || (pReg == NULL)) {
printk("Wrong I2C write function\n");
return;
}
start_condition:
dev_id = (*pDEV_ID<<1) & 0xfe; //shift DEV_ID 1-bit left and unset in writting operation
reg = *pReg;
data_hibyte =(unsigned char) (*pData>>8);
data_lowbyte =(unsigned char) (*pData & 0xff);
#if 1
i2c_start_condition( pI2C_Dev );
#else
__i2c_initGpioPin(pI2C_Dev->sdio, GPIO_DIR_OUT, GPIO_INT_DISABLE);//change sdio to output
__i2c_setGpioDataBit( pI2C_Dev->sdio, 1); /* raise sdio*/
__i2c_setGpioDataBit( pI2C_Dev->sclk, 1); /* raise sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sdio, 0); /* fall down sdio*//*start condition*/
//delay 2 us.
#ifdef __kernel_used__
udelay(2*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<2000*I2C_RATING_FACTOR;i++);
#endif
#endif
i2c_serial_write(pI2C_Dev,&dev_id);//write pDEV_ID,from MSB to LSB
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition;
i2c_serial_write(pI2C_Dev,®);//write pReg,from MSB to LSB
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition;
i2c_serial_write(pI2C_Dev,&data_hibyte);//write pData(hibtye),from MSB to LSB (bit15 - bit 8)
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition;
i2c_serial_write(pI2C_Dev,&data_lowbyte);//write pData(lowbtye),from MSB to LSB (bit7 - bit 0)
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition;
#if 1
i2c_stop_condition( pI2C_Dev );
#else
__i2c_setGpioDataBit( pI2C_Dev->sclk, 0); /* fall down sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sclk, 1); /* raise sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_initGpioPin(pI2C_Dev->sdio, GPIO_DIR_OUT, GPIO_INT_DISABLE);//change sdio to output
__i2c_setGpioDataBit( pI2C_Dev->sdio, 1); /* raise sdio*//*stop condition*/
#endif
return;
}
/*
@func int | _rtl865xC_i2c_rawRead | Read several bits from device
@parm i2c_dev_t* | pI2C_Dev | Structure containing device information
@parm unsigned char* | pDEV_ID | i2c id address
@parm unsigned char* | pReg | i2c register address
@parm unsigned short int* | pData | i2c data
@comm
*/
static void __i2c_rawRead_alc5621( i2c_dev_t* pI2C_Dev, const unsigned char *pDEV_ID, unsigned char *pReg, unsigned short int *pData)
{
int i;
unsigned short int buf;
unsigned char dev_id, reg;
if ((pData == NULL) || (pDEV_ID == NULL) || (pReg == NULL)) {
printk("Wrong I2C Read function\n");
return;
}
start_condition_read:
//dev_id = (*pDEV_ID<<1) | 0x01; //shift DEV_ID 1-bit left and set bit0 in reading operation
dev_id = (*pDEV_ID<<1) & 0xfe; //shift DEV_ID 1-bit left and unset in writting operation
reg = *pReg;
*pData = 0;
#if 1
i2c_start_condition( pI2C_Dev );
#else
__i2c_initGpioPin(pI2C_Dev->sdio, GPIO_DIR_OUT, GPIO_INT_DISABLE);//change sdio to output
__i2c_setGpioDataBit( pI2C_Dev->sdio, 1); /* raise sdio*/
__i2c_setGpioDataBit( pI2C_Dev->sclk, 1); /* raise sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sdio, 0); /* fall down sdio*//*start condition*/
//delay 2 us.
#ifdef __kernel_used__
udelay(2*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<2000*I2C_RATING_FACTOR;i++);
#endif
#endif
i2c_serial_write(pI2C_Dev,&dev_id);//write pDEV_ID,from MSB to LSB
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition_read;
i2c_serial_write(pI2C_Dev,®);//write pReg,from MSB to LSB
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition_read;
#if 1
i2c_start_condition( pI2C_Dev );
#else
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_initGpioPin(pI2C_Dev->sdio, GPIO_DIR_OUT, GPIO_INT_DISABLE);//change sdio to output
__i2c_setGpioDataBit( pI2C_Dev->sdio, 1); /* raise sdio*/
__i2c_setGpioDataBit( pI2C_Dev->sclk, 1); /* raise sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sdio, 0); /* fall down sdio*//*start condition*/
//delay 2 us.
#ifdef __kernel_used__
udelay(2*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<2000*I2C_RATING_FACTOR;i++);
#endif
#endif
dev_id = (*pDEV_ID<<1) | 0x01; //shift DEV_ID 1-bit left and set bit0 in reading operation
i2c_serial_write(pI2C_Dev,&dev_id);//write pDEV_ID,from MSB to LSB
if (i2c_ACK(pI2C_Dev) != 0)
goto start_condition_read;
buf=0; //init buf data to 0
i2c_serial_read(pI2C_Dev,&buf);//read high byte data from device
i2c_ACK_w(pI2C_Dev, 0); //write ACK
i2c_serial_read(pI2C_Dev,pData);//read low byte data from device
i2c_ACK_w(pI2C_Dev, 1); //write NACK
*pData = *pData | (buf <<8);
#if 1
i2c_stop_condition( pI2C_Dev );
#else
__i2c_initGpioPin(pI2C_Dev->sdio, GPIO_DIR_OUT, GPIO_INT_DISABLE);//change sdio to output
__i2c_setGpioDataBit( pI2C_Dev->sclk, 0); /* fall down sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sdio, 0); /* fall down sdio*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sclk, 1); /* raise sclk*/
//delay 1 us.
#ifdef __kernel_used__
udelay(1*I2C_RATING_FACTOR);
#endif
#ifdef __test_program_used__
for (i=0;i<1000*I2C_RATING_FACTOR;i++);
#endif
__i2c_setGpioDataBit( pI2C_Dev->sdio, 1); /* raise sdio*//*stop condition*/
#endif
return;
}
/*
* IRQ handler for I2C master. Handles transmission/reception.
*/
void _i2c_irq_handler(i2c_dev *dev) {
static uint8_t received_bytes;
i2c_msg *msg = dev->msg;
fooprint("inside interrupt");
// true if this is a receive intruction
uint8 read = msg->flags & I2C_MSG_READ;
uint32_t controlReg = dev ->regs->CONTROL;
fooprint_int(controlReg);
/*
* Reset timeout counter
*/
dev->timestamp = systick_uptime();
/*
* Master needs to acknowledge after recieving every byte and clear the acknowledge interrupt bit
*/
if (controlReg & I2C_CR_ACKI_MASK){
uint8_t bp,bc;
fooprint("ack condition");
received_bytes++; // there's a bug here if we have multiple msgs
fooprint("xferred");
fooprint_int(dev->msg->xferred);
fooprint("");
fooprint("received_bytes");
fooprint_int(received_bytes);
fooprint("");
fooprint("msg_length");
fooprint_int(dev->msg->length);
fooprint("");
fooprint("msgs_left");
fooprint_int(dev->msgs_left);
fooprint("");
if ((dev->msg->xferred + received_bytes == dev->msg->length) &&
(dev->msgs_left==1)) {
dev->regs->CONTROL &=~I2C_CR_ACK_MASK;
fooprint("last byte, sending NACK");
} else {
fooprint("more bytes expected, sending ACK");
dev->regs->CONTROL |=I2C_CR_ACK_MASK;
}
dev->regs->CONTROL &= ~I2C_CR_ACKI_MASK;
return;
}
/*
* Stop Condition Sent
*/
if (controlReg & I2C_CR_STOI_MASK){
fooprint("stop condition");
dev->state = I2C_STATE_XFER_DONE;
dev->regs->CONTROL &= ~I2C_CR_STO_MASK;
dev->regs->CONTROL &= ~I2C_CR_STOI_MASK;
return;
}
/*
* EV5: Start condition sent
*/
if (controlReg & I2C_CR_STAI_MASK) {
fooprint("start condition");
msg->xferred = 0;
//i2c_enable_irq(dev, I2C_IRQ_BUFFER);
// clear Start bit (sta) and
dev->regs->CONTROL &= (~I2C_CR_STA_MASK);
/*
* Master receiver
*/
//???????????????????????????????????????????????????????????????
// enable an acknowledge interrupt
if (read) {
i2c_enable_ack(dev);
}
dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK;
dev->regs->CONFIG |= 1 << I2C_CFGR_BC_BIT;
// sets the slave address and read/write direction
i2c_send_slave_addr(dev, msg->addr, read);
controlReg = 0;
// set the arm transmit bit to enable transmission of message
dev->regs->CONTROL |= I2C_CR_TXARM_MASK;
// clear start interrupt flag(STAI) bit
dev->regs->CONTROL &= (~I2C_CR_STAI_MASK);
}
/*
* EV6: Slave address sent
*/
if (controlReg & I2C_CR_TXI_MASK) {
fooprint("transfer");
//if slave doesn't acknowledge generate a stop
if (!(controlReg & I2C_CR_ACK_MASK)){
fooprint("nack");
i2c_stop_condition(dev);
return;
}
fooprint(" no nack");
if (read) {
received_bytes=0;
fooprint("transfer reading");
int32_t bytesLeft = msg->length - msg->xferred;
if (bytesLeft >= 4){
bytesLeft = 4;
}
dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK;
if (bytesLeft < 4) {
dev->regs->CONFIG |= bytesLeft << I2C_CFGR_BC_BIT;
}
// set the receive arm interrupt bit
dev->regs->CONTROL |= I2C_CR_RXARM_MASK;
// clear the transmit interrupt flag
dev->regs->CONTROL &= (~I2C_CR_TXI_MASK);
} else {
fooprint("transfer writing");
int32_t bytesLeft = msg->length - msg->xferred;
// if the last byte is transferred and there are no more messages generate a stop condition
if (!bytesLeft) {
if (--dev->msgs_left)
dev->msg++;
}
if (bytesLeft == 0 && dev->msgs_left == 0){
fooprint("tx done, generating stop");
i2c_stop_condition(dev);
// clear the transmit interrupt flag
dev->regs->CONTROL &= (~I2C_CR_TXI_MASK);
return;
}
// are no more bytes to transfer and there are messages do a repeated start
else if(bytesLeft == 0){
fooprint("transfer repeated start");
i2c_start_condition(dev);
// clear the transmit interrupt flag
dev->regs->CONTROL &= (~I2C_CR_TXI_MASK);
// clear the transmit interrupt flag
dev->regs->CONTROL &= (~I2C_CR_TXI_MASK);
return;
}
if (bytesLeft >= 4){
bytesLeft = 4;
}
fooprint("bytes left:");
fooprint_int(bytesLeft);
fooprint("");
//clear BC bits
dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK;
if (bytesLeft < 4) {
dev->regs->CONFIG |= bytesLeft << I2C_CFGR_BC_BIT;
}
fooprint("CONFIG");
fooprint_int(dev->regs->CONFIG);
fooprint("");
// load the data Buffer
i2c_write(dev, bytesLeft);
fooprint("DATA");
fooprint_int(dev->regs->DATA);
fooprint("");
// set the arm transmit bit to enable transmission of message
dev->regs->CONTROL |= I2C_CR_TXARM_MASK;
// clear the transmit interrupt flag
dev->regs->CONTROL &= (~I2C_CR_TXI_MASK);
}
fooprint("transfer done");
}
/*
* EV7: Master Receiver
*/
if (controlReg & I2C_CR_RXI_MASK) {
fooprint("receive");
uint32_t start = dev->msg->xferred;
uint8_t bytes = (dev->regs->CONFIG & I2C_CFGR_BC_MASK) >> I2C_CFGR_BC_BIT;
if (!bytes)
bytes = 4;
fooprint("bytes");
fooprint_int(bytes);
fooprint("");
memcpy(&dev->msg->data[start], &dev->regs->DATA, bytes);
dev->msg->xferred += bytes;
start = dev->msg->xferred;
received_bytes=0;
fooprint("xferred");
fooprint_int(dev->msg->xferred);
fooprint("");
int32_t bytesLeft = msg->length - msg->xferred;
if (!bytesLeft) {
fooprint("rx: no bytes left");
dev->msgs_left--;
}
if (bytesLeft == 0 && dev->msgs_left == 0){
fooprint("rx: no msgs left, generating stop");
i2c_stop_condition(dev);
fooprint("rx: clearing rxi");
// clear the receive interrupt flag
dev->regs->CONTROL &= (~I2C_CR_RXI_MASK);
return;
}
// are no more bytes to transfer and there are messages do a repeated start
else if(bytesLeft == 0){
fooprint("rx: msgs left, repeated start");
// clear the receive interrupt flag
i2c_start_condition(dev);
dev->regs->CONTROL &= (~I2C_CR_RXI_MASK);
return;
}
if (bytesLeft >= 4){
//clear BC bits
bytesLeft = 4;
}
dev->regs->CONFIG &= ~I2C_CFGR_BC_MASK;
if (bytesLeft < 4) {
dev->regs->CONFIG |= bytesLeft << I2C_CFGR_BC_BIT;
}
// set the receive arm interrupt bit
dev->regs->CONTROL |= I2C_CR_RXARM_MASK;
dev->regs->CONTROL &= (~I2C_CR_RXI_MASK);
fooprint("rx: exit");
}