static int mdp_lcdc_probe(struct platform_device *pdev)
{
struct msm_lcdc_platform_data *pdata = pdev->dev.platform_data;
struct mdp_lcdc_info *lcdc;
int ret = 0;
#ifdef CONFIG_MSM_MDP40
struct mdp4_overlay_pipe *pipe;
int ptype;
#endif
if (!pdata) {
PR_DISP_ERR("%s: no LCDC platform data found\n", __func__);
return -EINVAL;
}
lcdc = kzalloc(sizeof(struct mdp_lcdc_info), GFP_KERNEL);
if (!lcdc)
return -ENOMEM;
/* We don't actually own the clocks, the mdp does. */
lcdc->mdp_clk = clk_get(mdp_dev->dev.parent, "mdp_clk");
if (IS_ERR(lcdc->mdp_clk)) {
PR_DISP_ERR("%s: failed to get mdp_clk\n", __func__);
ret = PTR_ERR(lcdc->mdp_clk);
goto err_get_mdp_clk;
}
lcdc->pclk = clk_get(mdp_dev->dev.parent, "lcdc_pclk_clk");
if (IS_ERR(lcdc->pclk)) {
PR_DISP_ERR("%s: failed to get lcdc_pclk\n", __func__);
ret = PTR_ERR(lcdc->pclk);
goto err_get_pclk;
}
lcdc->pad_pclk = clk_get(mdp_dev->dev.parent, "lcdc_pad_pclk_clk");
if (IS_ERR(lcdc->pad_pclk)) {
PR_DISP_ERR("%s: failed to get lcdc_pad_pclk\n", __func__);
ret = PTR_ERR(lcdc->pad_pclk);
goto err_get_pad_pclk;
}
init_waitqueue_head(&lcdc->vsync_waitq);
lcdc->pdata = pdata;
lcdc->frame_start_cb.func = lcdc_frame_start;
platform_set_drvdata(pdev, lcdc);
#ifdef CONFIG_MSM_MDP40
mdp_out_if_register(mdp_dev, MSM_LCDC_INTERFACE, lcdc, INTR_OVERLAY0_DONE,
lcdc_overlay_start);
#else
mdp_out_if_register(mdp_dev, MSM_LCDC_INTERFACE, lcdc, MDP_DMA_P_DONE,
lcdc_dma_start);
#endif
lcdc->mdp = container_of(mdp_dev, struct mdp_info, mdp_dev);
precompute_timing_parms(lcdc);
lcdc->fb_start = pdata->fb_resource->start;
//lcdc->mdp = container_of(mdp_dev, struct mdp_info, mdp_dev);
if(lcdc->mdp->mdp_dev.color_format)
lcdc->color_format = lcdc->mdp->mdp_dev.color_format;
else
lcdc->color_format = MSM_MDP_OUT_IF_FMT_RGB565;
#ifdef CONFIG_MSM_MDP40
if (lcdc_pipe == NULL) {
ptype = mdp4_overlay_format2type(MDP_RGB_565);
pipe = mdp4_overlay_pipe_alloc(ptype, false);
if (!pipe)
goto err_mdp4_overlay_pipe_alloc;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->pipe_used = 1;
pipe->mixer_num = MDP4_MIXER0;
pipe->src_format = MDP_RGB_565;
mdp4_overlay_format2pipe(pipe);
pipe->mdp = lcdc->mdp;
lcdc_pipe = pipe; /* keep it */
} else {
pipe = lcdc_pipe;
}
pipe->src_height = pdata->fb_data->yres;
pipe->src_width = pdata->fb_data->xres;
pipe->src_h = pdata->fb_data->yres;
pipe->src_w = pdata->fb_data->xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->srcp0_addr = (uint32_t) lcdc->fb_start;
pipe->srcp0_ystride = pdata->fb_data->xres * 2;
mdp4_overlay_rgb_setup(pipe);
mdp4_mixer_stage_up(pipe);
#endif
lcdc->fb_panel_data.suspend = lcdc_suspend;
lcdc->fb_panel_data.resume = lcdc_resume;
lcdc->fb_panel_data.wait_vsync = lcdc_wait_vsync;
lcdc->fb_panel_data.request_vsync = lcdc_request_vsync;
lcdc->fb_panel_data.clear_vsync = lcdc_clear_vsync;
lcdc->fb_panel_data.blank = lcdc_blank;
lcdc->fb_panel_data.unblank = lcdc_unblank;
lcdc->fb_panel_data.fb_data = pdata->fb_data;
lcdc->fb_panel_data.interface_type = MSM_LCDC_INTERFACE;
lcdc->fb_panel_data.shutdown = lcdc_shutdown;
ret = lcdc_hw_init(lcdc);
if (ret) {
PR_DISP_ERR("%s: Cannot initialize the mdp_lcdc\n", __func__);
goto err_hw_init;
}
lcdc->fb_pdev.name = "msm_panel";
lcdc->fb_pdev.id = pdata->fb_id;
lcdc->fb_pdev.resource = pdata->fb_resource;
lcdc->fb_pdev.num_resources = 1;
lcdc->fb_pdev.dev.platform_data = &lcdc->fb_panel_data;
ret = platform_device_register(&lcdc->fb_pdev);
if (ret) {
PR_DISP_ERR("%s: Cannot register msm_panel pdev\n", __func__);
goto err_plat_dev_reg;
}
PR_DISP_INFO("%s: initialized\n", __func__);
#ifdef CONFIG_PANEL_SELF_REFRESH
if (lcdc->mdp->mdp_dev.overrides & MSM_MDP_RGB_PANEL_SELE_REFRESH) {
ret = icm_init(lcdc);
if (ret) {
PR_DISP_ERR("%s: Cannot init dispaly selfrefresh \n", __func__);
goto err_plat_dev_reg;
}
}
#endif
return 0;
err_plat_dev_reg:
err_hw_init:
#ifdef CONFIG_MSM_MDP40
err_mdp4_overlay_pipe_alloc:
#endif
platform_set_drvdata(pdev, NULL);
clk_put(lcdc->pad_pclk);
err_get_pad_pclk:
clk_put(lcdc->pclk);
err_get_pclk:
clk_put(lcdc->mdp_clk);
err_get_mdp_clk:
kfree(lcdc);
return ret;
}
/**
* \brief Application entry point for ICM example.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* ICM configuration */
struct icm_config icm_cfg;
/* Initialize the SAM system */
sysclk_init();
board_init();
sleepmgr_init();
/* Initialize the console uart */
configure_console();
/* Output example information */
printf("-- ICM Example --\r\n");
printf("-- %s\n\r", BOARD_NAME);
printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
/* ICM initialization */
icm_cfg.is_write_back= false;
icm_cfg.is_dis_end_mon = false;
icm_cfg.is_sec_list_branch = false;
icm_cfg.bbc = 0;
icm_cfg.is_auto_mode = false;
icm_cfg.is_dual_buf = false;
icm_cfg.is_user_hash = false;
icm_cfg.ualgo = ICM_SHA_1;
icm_cfg.hash_area_val = 0;
icm_cfg.des_area_val = 0;
icm_init(ICM, &icm_cfg);
/* Set region0 descriptor */
reg_descriptor[0].start_addr = (uint32_t)message_sha_0;
reg_descriptor[0].cfg.is_compare_mode = false;
reg_descriptor[0].cfg.is_wrap = false;
reg_descriptor[0].cfg.is_end_mon = false;
reg_descriptor[0].cfg.reg_hash_int_en = false;
reg_descriptor[0].cfg.dig_mis_int_en = false;
reg_descriptor[0].cfg.bus_err_int_en = false;
reg_descriptor[0].cfg.wrap_con_int_en = false;
reg_descriptor[0].cfg.ebit_con_int_en = false;
reg_descriptor[0].cfg.status_upt_con_int_en = false;
reg_descriptor[0].cfg.is_pro_dly = false;
reg_descriptor[0].cfg.mem_reg_val = 0;
reg_descriptor[0].cfg.algo = ICM_SHA_1;
reg_descriptor[0].tran_size = 0;
reg_descriptor[0].next_addr = 0;
/* Set region1 descriptor in main list */
reg_descriptor[1].start_addr = (uint32_t)message_sha_1_main;
reg_descriptor[1].cfg.is_compare_mode = false;
reg_descriptor[1].cfg.is_wrap = false;
reg_descriptor[1].cfg.is_end_mon = true;
reg_descriptor[1].cfg.reg_hash_int_en = false;
reg_descriptor[1].cfg.dig_mis_int_en = false;
reg_descriptor[1].cfg.bus_err_int_en = false;
reg_descriptor[1].cfg.wrap_con_int_en = false;
reg_descriptor[1].cfg.ebit_con_int_en = false;
reg_descriptor[1].cfg.status_upt_con_int_en = false;
reg_descriptor[1].cfg.is_pro_dly = false;
reg_descriptor[1].cfg.mem_reg_val = 0;
reg_descriptor[1].cfg.algo = ICM_SHA_1;
reg_descriptor[1].tran_size = 0;
reg_descriptor[1].next_addr = ®_descriptor_sec;
/* Set region1 descriptor in secondary list */
reg_descriptor_sec.start_addr = (uint32_t)message_sha_1_sec;
reg_descriptor_sec.tran_size = 0;
reg_descriptor_sec.next_addr = 0;
/* Set region descriptor start address */
icm_set_reg_des_addr(ICM, (uint32_t)®_descriptor[0]);
/* Set hash area start address */
icm_set_hash_area_addr(ICM, (uint32_t)output_sha);
/* Enable ICM */
icm_enable(ICM);
delay_ms(200);
/* Set region monitoring mode to compare mode */
reg_descriptor[0].cfg.is_compare_mode = true;
reg_descriptor[1].cfg.is_compare_mode = true;
/* Set callback function for digest mismatch interrupt handler */
icm_set_callback(ICM, reg_dig_mismatch_handler, ICM_REGION_NUM_0,
ICM_INTERRUPT_RDM, 1);
icm_set_callback(ICM, reg_dig_mismatch_handler, ICM_REGION_NUM_1,
ICM_INTERRUPT_RDM, 1);
/* Modify memory region value */
message_sha_0[0] = 0x12345678;
message_sha_1_sec[0] = 0x12345678;
/* Enable ICM */
icm_enable(ICM);
while (1) {
}
}
