Ejemplo n.º 1
0
static void init_fec2_ioports(struct fs_platform_info *ptr)
{
	cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
	iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);

	/* configure FEC2 pins */
	setbits32(&cp->cp_pepar, 0x0003fffc);
	setbits32(&cp->cp_pedir, 0x0003fffc);
	clrbits32(&cp->cp_peso, 0x000087fc);
	setbits32(&cp->cp_peso, 0x00037800);
	clrbits32(&cp->cp_cptr, 0x00000080);

	immr_unmap(io_port);
	immr_unmap(cp);
}
Ejemplo n.º 2
0
void smc1_lineif(struct uart_cpm_port *pinfo)
{
	/* XXX SMC1: insert port configuration here */
	unsigned *bcsr_io;
	cpm8xx_t *cp;
	pinfo->brg = 1;

#if defined (CONFIG_MPC885ADS) || defined (CONFIG_MPC86XADS)
#if defined(CONFIG_MPC885ADS)
	cp = (cpm8xx_t *)immr_map(im_cpm);
	setbits32(&cp->cp_pepar, 0x000000c0);
	clrbits32(&cp->cp_pedir, 0x000000c0);
	clrbits32(&cp->cp_peso, 0x00000040);
	setbits32(&cp->cp_peso, 0x00000080);
	immr_unmap(cp);
#endif

	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));

	if (bcsr_io == NULL) {
		printk(KERN_CRIT "Could not remap BCSR\n");
		return;
	}
	out_be32(bcsr_io, in_be32(bcsr_io) & ~BCSR1_RS232EN_1);
	iounmap(bcsr_io);
#endif
}
Ejemplo n.º 3
0
void __init cpm_reset(void)
{
	sysconf8xx_t __iomem *siu_conf;

	mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
	if (!mpc8xx_immr) {
		printk(KERN_CRIT "Could not map IMMR\n");
		return;
	}

	cpmp = &mpc8xx_immr->im_cpm;

#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
	out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);

	while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
#endif

#ifdef CONFIG_UCODE_PATCH
	cpm_load_patch(cpmp);
#endif

	siu_conf = immr_map(im_siu_conf);
	out_be32(&siu_conf->sc_sdcr, 1);
	immr_unmap(siu_conf);

	cpm_muram_init();
}
Ejemplo n.º 4
0
int mpc8xx_set_rtc_time(struct rtc_time *tm)
{
	sitk8xx_t __iomem *sys_tmr1;
	sit8xx_t __iomem *sys_tmr2;
	time64_t time;

	sys_tmr1 = immr_map(im_sitk);
	sys_tmr2 = immr_map(im_sit);
	time = rtc_tm_to_time64(tm);

	out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
	out_be32(&sys_tmr2->sit_rtc, (u32)time);
	out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);

	immr_unmap(sys_tmr2);
	immr_unmap(sys_tmr1);
	return 0;
}
Ejemplo n.º 5
0
int mpc8xx_set_rtc_time(struct rtc_time *tm)
{
	sitk8xx_t __iomem *sys_tmr1;
	sit8xx_t __iomem *sys_tmr2;
	int time;

	sys_tmr1 = immr_map(im_sitk);
	sys_tmr2 = immr_map(im_sit);
	time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
	              tm->tm_hour, tm->tm_min, tm->tm_sec);

	out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
	out_be32(&sys_tmr2->sit_rtc, time);
	out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);

	immr_unmap(sys_tmr2);
	immr_unmap(sys_tmr1);
	return 0;
}
Ejemplo n.º 6
0
init_internal_rtc(void)
{
	sit8xx_t __iomem *sys_tmr = immr_map(im_sit);

	/* Disable the RTC one second and alarm interrupts. */
	clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));

	/* Enable the RTC */
	setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
	immr_unmap(sys_tmr);
}
Ejemplo n.º 7
0
void mpc8xx_get_rtc_time(struct rtc_time *tm)
{
	unsigned long data;
	sit8xx_t __iomem *sys_tmr = immr_map(im_sit);

	/* Get time from the RTC. */
	data = in_be32(&sys_tmr->sit_rtc);
	rtc_time64_to_tm(data, tm);
	immr_unmap(sys_tmr);
	return;
}
Ejemplo n.º 8
0
static void init_fec1_ioports(struct fs_platform_info *ptr)
{
	cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
	iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);

	/* configure FEC1 pins  */
	setbits16(&io_port->iop_papar, 0xf830);
	setbits16(&io_port->iop_padir, 0x0830);
	clrbits16(&io_port->iop_padir, 0xf000);

	setbits32(&cp->cp_pbpar, 0x00001001);
	clrbits32(&cp->cp_pbdir, 0x00001001);

	setbits16(&io_port->iop_pcpar, 0x000c);
	clrbits16(&io_port->iop_pcdir, 0x000c);

	setbits32(&cp->cp_pepar, 0x00000003);
	setbits32(&cp->cp_pedir, 0x00000003);
	clrbits32(&cp->cp_peso, 0x00000003);
	clrbits32(&cp->cp_cptr, 0x00000100);

	immr_unmap(io_port);
	immr_unmap(cp);
}
Ejemplo n.º 9
0
Archivo: cpm1.c Proyecto: 1314cc/linux
void __init cpm_reset(void)
{
	sysconf8xx_t __iomem *siu_conf;

	mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
	if (!mpc8xx_immr) {
		printk(KERN_CRIT "Could not map IMMR\n");
		return;
	}

	cpmp = &mpc8xx_immr->im_cpm;

#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
	/* Perform a reset.
	*/
	out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);

	/* Wait for it.
	*/
	while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
#endif

#ifdef CONFIG_UCODE_PATCH
	cpm_load_patch(cpmp);
#endif

	/* Set SDMA Bus Request priority 5.
	 * On 860T, this also enables FEC priority 6.  I am not sure
	 * this is what we really want for some applications, but the
	 * manual recommends it.
	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
	 */
	siu_conf = immr_map(im_siu_conf);
	if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
		out_be32(&siu_conf->sc_sdcr, 0x40);
	else
		out_be32(&siu_conf->sc_sdcr, 1);
	immr_unmap(siu_conf);

	cpm_muram_init();
}
Ejemplo n.º 10
0
static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi)
{
	unsigned *bcsr_io;
	cpm8xx_t *cp;

	cp = (cpm8xx_t *) immr_map(im_cpm);
	setbits32(&cp->cp_pepar, 0x00000c00);
	clrbits32(&cp->cp_pedir, 0x00000c00);
	clrbits32(&cp->cp_peso, 0x00000400);
	setbits32(&cp->cp_peso, 0x00000800);
	immr_unmap(cp);

	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));

	if (bcsr_io == NULL) {
		printk(KERN_CRIT "Could not remap BCSR1\n");
		return;
	}
	clrbits32(bcsr_io, BCSR1_RS232EN_2);
	iounmap(bcsr_io);
}
Ejemplo n.º 11
0
void cpm_reset(void)
{
	cpm8xx_t	*commproc;
	sysconf8xx_t    *siu_conf;

	commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);

#ifdef CONFIG_UCODE_PATCH
	/* Perform a reset.
	*/
	out_be16(&commproc->cp_cpcr,  CPM_CR_RST | CPM_CR_FLG);

	/* Wait for it.
	*/
	while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);

	cpm_load_patch(commproc);
#endif

	/* Set SDMA Bus Request priority 5.
	 * On 860T, this also enables FEC priority 6.  I am not sure
	 * this is what we realy want for some applications, but the
	 * manual recommends it.
	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
	 */
	siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);
	out_be32(&siu_conf->sc_sdcr, 1);
	immr_unmap(siu_conf);

	/* Reclaim the DP memory for our use. */
	m8xx_cpm_dpinit();

	/* Tell everyone where the comm processor resides.
	*/
	cpmp = commproc;
}
Ejemplo n.º 12
0
/* The decrementer counts at the system (internal) clock frequency divided by
 * sixteen, or external oscillator divided by four.  We force the processor
 * to use system clock divided by sixteen.
 */
void __init mpc8xx_calibrate_decr(void)
{
	struct device_node *cpu;
	cark8xx_t __iomem *clk_r1;
	car8xx_t __iomem *clk_r2;
	sitk8xx_t __iomem *sys_tmr1;
	sit8xx_t __iomem *sys_tmr2;
	int irq, virq;

	clk_r1 = immr_map(im_clkrstk);

	/* Unlock the SCCR. */
	out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
	out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
	immr_unmap(clk_r1);

	/* Force all 8xx processors to use divide by 16 processor clock. */
	clk_r2 = immr_map(im_clkrst);
	setbits32(&clk_r2->car_sccr, 0x02000000);
	immr_unmap(clk_r2);

	/* Processor frequency is MHz.
	 */
	ppc_proc_freq = 50000000;
	if (!get_freq("clock-frequency", &ppc_proc_freq))
		printk(KERN_ERR "WARNING: Estimating processor frequency "
		                "(not found)\n");

	ppc_tb_freq = ppc_proc_freq / 16;
	printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);

	/* Perform some more timer/timebase initialization.  This used
	 * to be done elsewhere, but other changes caused it to get
	 * called more than once....that is a bad thing.
	 *
	 * First, unlock all of the registers we are going to modify.
	 * To protect them from corruption during power down, registers
	 * that are maintained by keep alive power are "locked".  To
	 * modify these registers we have to write the key value to
	 * the key location associated with the register.
	 * Some boards power up with these unlocked, while others
	 * are locked.  Writing anything (including the unlock code?)
	 * to the unlocked registers will lock them again.  So, here
	 * we guarantee the registers are locked, then we unlock them
	 * for our use.
	 */
	sys_tmr1 = immr_map(im_sitk);
	out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
	out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
	out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
	out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
	out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
	out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
	immr_unmap(sys_tmr1);

	init_internal_rtc();

	/* Enabling the decrementer also enables the timebase interrupts
	 * (or from the other point of view, to get decrementer interrupts
	 * we have to enable the timebase).  The decrementer interrupt
	 * is wired into the vector table, nothing to do here for that.
	 */
	cpu = of_find_node_by_type(NULL, "cpu");
	virq= irq_of_parse_and_map(cpu, 0);
	irq = virq_to_hw(virq);

	sys_tmr2 = immr_map(im_sit);
	out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
					(TBSCR_TBF | TBSCR_TBE));
	immr_unmap(sys_tmr2);

	if (setup_irq(virq, &tbint_irqaction))
		panic("Could not allocate timer IRQ!");
}
Ejemplo n.º 13
0
static void init_scc3_ioports(struct fs_platform_info *fpi)
{
	unsigned *bcsr_io;
	iop8xx_t *io_port;
	cpm8xx_t *cp;

	bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
	io_port = (iop8xx_t *) immr_map(im_ioport);
	cp = (cpm8xx_t *) immr_map(im_cpm);

	if (bcsr_io == NULL) {
		printk(KERN_CRIT "Could not remap BCSR\n");
		return;
	}

	/* Enable the PHY.
	 */
	clrbits32(bcsr_io + 4, BCSR4_ETH10_RST);
	udelay(1000);
	setbits32(bcsr_io + 4, BCSR4_ETH10_RST);
	/* Configure port A pins for Txd and Rxd.
	 */
	setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
	clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);

	/* Configure port C pins to enable CLSN and RENA.
	 */
	clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
	clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
	setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);

	/* Configure port E for TCLK and RCLK.
	 */
	setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
	clrbits32(&cp->cp_pepar, PE_ENET_TENA);
	clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
	clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
	setbits32(&cp->cp_peso, PE_ENET_TENA);

	/* Configure Serial Interface clock routing.
	 * First, clear all SCC bits to zero, then set the ones we want.
	 */
	clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
	setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);

	/* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
	 */
	clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
	/* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
	 * by H/W setting after reset. SCC ethernet controller support only half duplex.
	 * This discrepancy of modes causes a lot of carrier lost errors.
	 */

	/* In the original SCC enet driver the following code is placed at
	   the end of the initialization */
	setbits32(&cp->cp_pepar, PE_ENET_TENA);
	clrbits32(&cp->cp_pedir, PE_ENET_TENA);
	setbits32(&cp->cp_peso, PE_ENET_TENA);

	setbits32(bcsr_io + 4, BCSR1_ETHEN);
	iounmap(bcsr_io);
	immr_unmap(io_port);
	immr_unmap(cp);
}
Ejemplo n.º 14
0
void __init mpc885ads_board_setup(void)
{
	cpm8xx_t *cp;
	unsigned int *bcsr_io;
	u8 tmpval8;

#ifdef CONFIG_FS_ENET
	iop8xx_t *io_port;
#endif

	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
	cp = (cpm8xx_t *) immr_map(im_cpm);

	if (bcsr_io == NULL) {
		printk(KERN_CRIT "Could not remap BCSR\n");
		return;
	}
#ifdef CONFIG_SERIAL_CPM_SMC1
	clrbits32(bcsr_io, BCSR1_RS232EN_1);
	clrbits32(&cp->cp_simode, 0xe0000000 >> 17);	/* brg1 */
	tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
	out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
	clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);	/* brg1 */
#else
	setbits32(bcsr_io, BCSR1_RS232EN_1);
	out_be16(&cp->cp_smc[0].smc_smcmr, 0);
	out_8(&cp->cp_smc[0].smc_smce, 0);
#endif

#ifdef CONFIG_SERIAL_CPM_SMC2
	clrbits32(bcsr_io, BCSR1_RS232EN_2);
	clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
	setbits32(&cp->cp_simode, 0x20000000 >> 1);	/* brg2 */
	tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
	out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
	clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);

	init_smc2_uart_ioports(0);
#else
	setbits32(bcsr_io, BCSR1_RS232EN_2);
	out_be16(&cp->cp_smc[1].smc_smcmr, 0);
	out_8(&cp->cp_smc[1].smc_smce, 0);
#endif
	immr_unmap(cp);
	iounmap(bcsr_io);

#ifdef CONFIG_FS_ENET
	/* use MDC for MII (common) */
	io_port = (iop8xx_t *) immr_map(im_ioport);
	setbits16(&io_port->iop_pdpar, 0x0080);
	clrbits16(&io_port->iop_pddir, 0x0080);

	bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
	clrbits32(bcsr_io, BCSR5_MII1_EN);
	clrbits32(bcsr_io, BCSR5_MII1_RST);
#ifndef CONFIG_FC_ENET_HAS_SCC
	clrbits32(bcsr_io, BCSR5_MII2_EN);
	clrbits32(bcsr_io, BCSR5_MII2_RST);

#endif
	iounmap(bcsr_io);
	immr_unmap(io_port);

#endif

#ifdef CONFIG_PCMCIA_M8XX
	/*Set up board specific hook-ups */
	m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
	m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
#endif
}