static void print_fpga_info(void) { struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; unsigned feature_expansion; unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; feature_expansion = fpga_features & (1<<15); puts("FPGA: "); switch (unit_type) { case UNITTYPE_CCD_SWITCH: printf("CCD-Switch"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_100: printf(" HW-Ver 1.00\n"); break; case HWVER_110: printf(" HW-Ver 1.10\n"); break; case HWVER_121: printf(" HW-Ver 1.21\n"); break; case HWVER_122: printf(" HW-Ver 1.22\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); printf(" %d channel(s)", feature_channels); printf(", expansion %ssupported\n", feature_expansion ? "" : "un"); }
static void ace_datain_be16(struct ace_device *ace) { int i = ACE_FIFO_SIZE / 2; u16 *dst = ace->data_ptr; while (i--) #if defined(CONFIG_PLAT_MILKYMIST) && defined(CONFIG_BOARD_XILINX_ML401) *dst++ = in_le16(ace->baseaddr + 0x82); #else *dst++ = in_le16(ace->baseaddr + 0x40); #endif ace->data_ptr = dst; }
static void print_fpga_info(void) { struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0); u16 versions = in_le16(&fpga->versions); u16 fpga_version = in_le16(&fpga->fpga_version); u16 fpga_features = in_le16(&fpga->fpga_features); int fpga_state = get_fpga_state(0); unsigned unit_type; unsigned hardware_version; unsigned feature_channels; puts("FPGA: "); if (fpga_state & FPGA_STATE_DONE_FAILED) { printf(" done timed out\n"); return; } if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { printf(" refelectione test failed\n"); return; } unit_type = (versions & 0xf000) >> 12; hardware_version = versions & 0x000f; feature_channels = fpga_features & 0x007f; switch (unit_type) { case UNITTYPE_CCX16: printf("CCX-Switch"); break; default: printf("UnitType %d(not supported)", unit_type); break; } switch (hardware_version) { case HWVER_300: printf(" HW-Ver 3.00-3.12\n"); break; default: printf(" HW-Ver %d(not supported)\n", hardware_version); break; } printf(" FPGA V %d.%02d, features:", fpga_version / 100, fpga_version % 100); printf(" %d channel(s)\n", feature_channels); }
static int prep_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = bus->sysdata; volatile void __iomem *cfg_data; if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR || DEVNO(devfn) > MAX_DEVNR) return PCIBIOS_DEVICE_NOT_FOUND; /* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4. */ cfg_data = hose->cfg_data + CFGADDR(devfn) + offset; switch (len) { case 1: *val = in_8(cfg_data); break; case 2: *val = in_le16(cfg_data); break; default: *val = in_le32(cfg_data); break; } return PCIBIOS_SUCCESSFUL; }
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, int offset, int len, u32 *val) { *val = 0; /* * 440SPE implements only one function per port */ if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1))) return 0; devfn = PCI_BDF(0,0,0); offset += devfn << 4; switch (len) { case 1: *val = in_8(hose->cfg_data + offset); break; case 2: *val = in_le16((u16 *)(hose->cfg_data + offset)); break; default: *val = in_le32((u32 *)(hose->cfg_data + offset)); break; } return 0; }
int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, int len, u32 *val) { volatile void __iomem *cfg_data; struct pci_controller *hose = bus->sysdata; if (bus->number > 7) return PCIBIOS_DEVICE_NOT_FOUND; /* * Note: the caller has already checked that off is * suitably aligned and that len is 1, 2 or 4. */ cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); switch (len) { case 1: *val = in_8(cfg_data); break; case 2: *val = in_le16(cfg_data); break; default: *val = in_le32(cfg_data); break; } return PCIBIOS_SUCCESSFUL; }
static int pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = bus->sysdata; if (PCI_SLOT(devfn) != 1) return PCIBIOS_DEVICE_NOT_FOUND; offset += devfn << 12; /* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4. */ switch (len) { case 1: *val = in_8(hose->cfg_data + offset); break; case 2: *val = in_le16(hose->cfg_data + offset); break; default: *val = in_le32(hose->cfg_data + offset); break; } if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset); return PCIBIOS_SUCCESSFUL; }
void __pci_target_init(struct pci_controller * hose) { /* * Disable everything */ out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ /* * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options do not support sizes such as 128/256 MB. */ out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); out_le32((void *)PCIL0_PIM0LAH, 0); out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); out_le32((void *)PCIL0_BAR0, 0); /* * Program the board's subsystem id/vendor id */ out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) | PCI_COMMAND_MEMORY); }
static int celleb_epci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { PCI_IO_ADDR epci_base; PCI_IO_ADDR addr; struct pci_controller *hose = pci_bus_to_host(bus); /* allignment check */ BUG_ON(where % size); if (!celleb_epci_get_epci_cfg(hose)) return PCIBIOS_DEVICE_NOT_FOUND; if (bus->number == hose->first_busno && devfn == 0) { /* EPCI controller self */ epci_base = celleb_epci_get_epci_base(hose); addr = epci_base + where; switch (size) { case 1: *val = in_8(addr); break; case 2: *val = in_be16(addr); break; case 4: *val = in_be32(addr); break; default: return PCIBIOS_DEVICE_NOT_FOUND; } } else { clear_and_disable_master_abort_interrupt(hose); addr = celleb_epci_make_config_addr(bus, hose, devfn, where); switch (size) { case 1: *val = in_8(addr); break; case 2: *val = in_le16(addr); break; case 4: *val = in_le32(addr); break; default: return PCIBIOS_DEVICE_NOT_FOUND; } } pr_debug("EPCI: " "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n", addr, devfn, where, size, *val); return celleb_epci_check_abort(hose, NULL); }
static void ace_datain_be16(struct ace_device *ace) { int i = ACE_FIFO_SIZE / 2; u16 *dst = ace->data_ptr; while (i--) *dst++ = in_le16(ace->baseaddr + 0x40); ace->data_ptr = dst; }
static int indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; u8 cfg_type = 0; u32 bus_no, reg; if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) { if (bus->number != hose->first_busno) return PCIBIOS_DEVICE_NOT_FOUND; if (devfn != 0) return PCIBIOS_DEVICE_NOT_FOUND; } if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) if (bus->number != hose->first_busno) cfg_type = 1; bus_no = (bus->number == hose->first_busno) ? hose->self_busno : bus->number; if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG) reg = ((offset & 0xf00) << 16) | (offset & 0xfc); else reg = offset & 0xfc; if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); else out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); /* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4. */ cfg_data = hose->cfg_data + (offset & 3); switch (len) { case 1: *val = in_8(cfg_data); break; case 2: *val = in_le16(cfg_data); break; default: *val = in_le32(cfg_data); break; } return PCIBIOS_SUCCESSFUL; }
static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); struct ppc4xx_pciex_port *port = &ppc4xx_pciex_ports[hose->indirect_type]; void __iomem *addr; u32 gpl_cfg; BUG_ON(hose != port->hose); if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) return PCIBIOS_DEVICE_NOT_FOUND; addr = ppc4xx_pciex_get_config_base(port, bus, devfn); /* * Reading from configuration space of non-existing device can * generate transaction errors. For the read duration we suppress * assertion of machine check exceptions to avoid those. */ gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); /* Make sure no CRS is recorded */ out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); switch (len) { case 1: *val = in_8((u8 *)(addr + offset)); break; case 2: *val = in_le16((u16 *)(addr + offset)); break; default: *val = in_le32((u32 *)(addr + offset)); break; } pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", bus->number, hose->first_busno, hose->last_busno, devfn, offset, len, addr + offset, *val); /* Check for CRS (440SPe rev B does that for us but heh ..) */ if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { pr_debug("Got CRS !\n"); if (len != 4 || offset != 0) return PCIBIOS_DEVICE_NOT_FOUND; *val = 0xffff0001; } dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); return PCIBIOS_SUCCESSFUL; }
int gg2_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { if (bus > 7) { *val = 0xffff; return PCIBIOS_DEVICE_NOT_FOUND; } *val = in_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset)); return PCIBIOS_SUCCESSFUL; }
int gd405ex_get_fpga_done(unsigned fpga) { int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM; if (legacy) return in_le16((void *)LATCH3_BASE) & CONFIG_SYS_FPGA_DONE(fpga); else return pca9698_get_value(0x22, fpga ? 9 : 8); }
int readw(volatile unsigned short *addr) { u16 val; unsigned long pa = iopa((unsigned long) addr); if (!is_pci_mem(pa)) return in_le16(addr); idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0); return swab16(val); }
static int indirect_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, uint16_t *val) { HOSE_PREAMBLE; *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; out_be32((unsigned int*) pci.pci_config_addr, 0x80|(bus<<8)|(PCI_DEVFN(slot,function)<<16)|((offset&~3)<<24)); *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3))); return PCIBIOS_SUCCESSFUL; }
int raven_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn, unsigned char offset, unsigned short *val) { if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND; if (offset&1)return PCIBIOS_BAD_REGISTER_NUMBER; out_be32(pci_config_address, 0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24)); *val = in_le16((volatile unsigned short *) (pci_config_data+(offset&3))); return PCIBIOS_SUCCESSFUL; }
/* read from bus/slot/fn 0/0/0 */ static unsigned long pci_early_config_read(int offset, int width) { out_be32((unsigned int*) pci.pci_config_addr, 0x80|(0<<8)|(PCI_DEVFN(0,0)<<16)|((offset&~3)<<24)); switch (width) { default: case 1: return in_8((unsigned char*)pci.pci_config_data + (offset&3)); case 2: return in_le16((unsigned short*)pci.pci_config_data + (offset&3)); case 4: return in_le32((unsigned long *)pci.pci_config_data + (offset&3)); } }
static int indirect_pci_read_config_word( unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, uint16_t *val ) { *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset); *val = in_le16((volatile unsigned short *)(pci.pci_config_data + (offset&3))); return PCIBIOS_SUCCESSFUL; }
static int direct_pci_read_config_word( unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, uint16_t *val ) { *val = 0xffff; if (offset&1) return PCIBIOS_BAD_REGISTER_NUMBER; if (bus != 0 || (1<<slot & 0xff8007fe)) return PCIBIOS_DEVICE_NOT_FOUND; *val=in_le16((volatile unsigned short *) (pci.pci_config_data + ((1<<slot)&~1) + (function<<8) + offset)); return PCIBIOS_SUCCESSFUL; }
/* * return the current pointer */ inline static snd_pcm_uframes_t snd_pmac_pcm_pointer(struct snd_pmac *chip, struct pmac_stream *rec, struct snd_pcm_substream *subs) { int count = 0; #if 1 /* hmm.. how can we get the current dma pointer?? */ int stat; volatile struct dbdma_cmd __iomem *cp = &rec->cmd.cmds[rec->cur_period]; stat = le16_to_cpu(cp->xfer_status); if (stat & (ACTIVE|DEAD)) { count = in_le16(&cp->res_count); if (count) count = rec->period_size - count; } #endif count += rec->cur_period * rec->period_size; /*printk(KERN_DEBUG "pointer=%d\n", count);*/ return bytes_to_frames(subs->runtime, count); }
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) { int res; switch (fpga) { case 0: *data = in_le16(reg); break; default: if (fpga > mclink_fpgacount) return -EINVAL; res = mclink_receive(fpga - 1, regoff, data); if (res < 0) { printf("mclink_receive reg %02lx returned %d\n", regoff, res); return res; } } return 0; }
static int mpc83xx_indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = bus->sysdata; volatile unsigned char *cfg_data; u8 cfg_type = 0; u8 bus_num; if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device(bus->number, devfn)) return PCIBIOS_DEVICE_NOT_FOUND; if (bus->number == hose->first_busno) bus_num = 0; else bus_num = bus->number; PCI_CFG_OUT(hose->cfg_addr, (0x80000000 | (bus_num << 16) | (devfn << 8) | ((offset & 0xfc) | cfg_type))); /* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4. */ cfg_data = hose->cfg_data + (offset & 3); switch (len) { case 1: *val = in_8((u8 *)cfg_data); break; case 2: *val = in_le16((u16 *)cfg_data); break; default: *val = in_le32((u32 *)cfg_data); break; } return PCIBIOS_SUCCESSFUL; }
static int mv_ata_exec_ata_cmd_nondma(int port, struct sata_fis_h2d *cfis, u8 *buffer, u32 len, u32 iswrite) { struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; int i; u16 *tp; debug("%s\n", __func__); out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count); out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high); out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid); out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low); out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features); out_le32(priv->regbase + PIO_DEVICE, cfis->device); out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command); if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS), ATA_BUSY, 0x0, 10000)) { debug("Failed to wait for completion\n"); return -1; } if (len > 0) { tp = (u16 *)buffer; for (i = 0; i < len / 2; i++) { if (iswrite) out_le16(priv->regbase + PIO_DATA, *tp++); else *tp++ = in_le16(priv->regbase + PIO_DATA); } } return len; }
static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port, struct pci_controller *hose, void __iomem *mbase, struct resource *res) { resource_size_t size = res->end - res->start + 1; u64 sa; if (port->endpoint) { resource_size_t ep_addr = 0; resource_size_t ep_size = 32 << 20; /* Currently we map a fixed 64MByte window to PLB address * 0 (SDRAM). This should probably be configurable via a dts * property. */ /* Calculate window size */ sa = (0xffffffffffffffffull << ilog2(ep_size)); /* Setup BAR0 */ out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) | PCI_BASE_ADDRESS_MEM_TYPE_64); /* Disable BAR1 & BAR2 */ out_le32(mbase + PECFG_BAR1MPA, 0); out_le32(mbase + PECFG_BAR2HMPA, 0); out_le32(mbase + PECFG_BAR2LMPA, 0); out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa)); out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa)); out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr)); out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr)); } else { /* Calculate window size */ sa = (0xffffffffffffffffull << ilog2(size)); if (res->flags & IORESOURCE_PREFETCH) sa |= 0x8; out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa)); out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa)); /* The setup of the split looks weird to me ... let's see * if it works */ out_le32(mbase + PECFG_PIM0LAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAH, 0x00000000); out_le32(mbase + PECFG_PIM1LAL, 0x00000000); out_le32(mbase + PECFG_PIM1LAH, 0x00000000); out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); out_le32(mbase + PECFG_PIM01SAL, 0x00000000); out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); } /* Enable inbound mapping */ out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16(mbase + PCI_COMMAND, in_le16(mbase + PCI_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); }
int board_early_init_r(void) { unsigned k; unsigned ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; /* * reset FPGA */ gd405ex_init(); gd405ex_set_fpga_reset(1); gd405ex_setup_hw(); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; while (!gd405ex_get_fpga_done(k)) { udelay(100000); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_DONE_FAILED; break; } } } udelay(10); gd405ex_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k); #ifdef CONFIG_SYS_FPGA_NO_RFL_HI u16 *reflection_target = &fpga->reflection_low; #else u16 *reflection_target = &fpga->reflection_high; #endif /* * wait for fpga out of reset */ ctr = 0; while (1) { out_le16(&fpga->reflection_low, REFLECTION_TESTPATTERN); if (in_le16(reflection_target) == REFLECTION_TESTPATTERN_INV) break; udelay(100000); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_REFLECTION_FAILED; break; } } } return 0; }
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data) { *data = in_le16(reg); return 0; }
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; int attempts = 0; pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, pcie_read_config_dword, pcie_write_config_byte, pcie_write_config_word, pcie_write_config_dword); switch (port) { case 0: mbase = (u32 *)CFG_PCIE0_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE; break; case 1: mbase = (u32 *)CFG_PCIE1_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; } /* * Set up outbound translation to hose->mem_space from PLB * addresses at an offset of 0xd_0000_0000. We set the low * bits of the mask to 11 to turn off splitting into 8 * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); out_le32(mbase + PECFG_POM0LAL, 0x00001000); switch (port) { case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE)); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + port * CFG_PCIE_MEMSIZE)); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(CFG_PCIE_MEMSIZE - 1) | 3); break; } /* Set up 16GB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); out_le32(mbase + PECFG_PIM0LAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ attempts = 10; switch (port) { case 0: while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { if (!(attempts--)) { printf("PCIE0: BMEN is not active\n"); return -1; } mdelay(1000); } break; case 1: while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { if (!(attempts--)) { printf("PCIE1: BMEN is not active\n"); return -1; } mdelay(1000); } break; case 2: while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { if (!(attempts--)) { printf("PCIE2: BMEN is not active\n"); return -1; } mdelay(1000); } break; } printf("PCIE:%d successfully set as endpoint\n",port); return 0; }
/* 16 bit little endian bus attachment */ static u16 ace_in_le16(struct ace_device *ace, int reg) { return in_le16(ace->baseaddr + reg); }
void ppc440spe_setup_pcie(struct pci_controller *hose, int port) { void __iomem *mbase; /* * Map 16MB, which is enough for 4 bits of bus # */ hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000, 1 << 24); hose->ops = &pcie_pci_ops; /* * Set bus numbers on our root port */ mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096); out_8(mbase + PCI_PRIMARY_BUS, 0); out_8(mbase + PCI_SECONDARY_BUS, 0); /* * Set up outbound translation to hose->mem_space from PLB * addresses at an offset of 0xd_0000_0000. We set the low * bits of the mask to 11 to turn off splitting into 8 * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0); out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start); switch (port) { case 0: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), ~(hose->mem_space.end - hose->mem_space.start) | 3); break; case 1: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), ~(hose->mem_space.end - hose->mem_space.start) | 3); break; case 2: mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), ~(hose->mem_space.end - hose->mem_space.start) | 3); break; } /* Set up 16GB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); out_le32(mbase + PECFG_BAR0LMPA, 0); out_le32(mbase + PECFG_PIM0LAL, 0); out_le32(mbase + PECFG_PIM0LAH, 0); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16(mbase + PCI_COMMAND, in_le16(mbase + PCI_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); iounmap(mbase); }