static int
aix5_in_dynsym_resolve_code (CORE_ADDR pc)
{
return ((pc >= interp_text_sect_low && pc < interp_text_sect_high)
|| (pc >= interp_plt_sect_low && pc < interp_plt_sect_high)
|| in_plt_section (pc, NULL));
}
static CORE_ADDR
arm_symbian_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
{
struct gdbarch *gdbarch;
enum bfd_endian byte_order;
ULONGEST insn;
CORE_ADDR dest;
gdb_byte buf[4];
if (!in_plt_section (pc))
return 0;
if (target_read_memory (pc, buf, 4) != 0)
return 0;
gdbarch = get_frame_arch (frame);
byte_order = gdbarch_byte_order (gdbarch);
/* ldr pc, [pc, #-4]. */
insn = extract_unsigned_integer (buf, 4, byte_order);
if (insn != 0xe51ff004)
return 0;
if (target_read_memory (pc + 4, buf, 4) != 0)
return 0;
dest = extract_unsigned_integer (buf, 4, byte_order);
return gdbarch_addr_bits_remove (gdbarch, dest);
}
static int
dsbt_in_dynsym_resolve_code (CORE_ADDR pc)
{
struct dsbt_info *info = get_dsbt_info ();
return ((pc >= info->interp_text_sect_low && pc < info->interp_text_sect_high)
|| (pc >= info->interp_plt_sect_low && pc < info->interp_plt_sect_high)
|| in_plt_section (pc, NULL));
}
CORE_ADDR
sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
struct sparc_frame_cache *cache)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
unsigned long insn;
int offset = 0;
int dest = -1;
if (current_pc <= pc)
return current_pc;
/* We have to handle to "Procedure Linkage Table" (PLT) special. On
SPARC the linker usually defines a symbol (typically
_PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
This symbol makes us end up here with PC pointing at the start of
the PLT and CURRENT_PC probably pointing at a PLT entry. If we
would do our normal prologue analysis, we would probably conclude
that we've got a frame when in reality we don't, since the
dynamic linker patches up the first PLT with some code that
starts with a SAVE instruction. Patch up PC such that it points
at the start of our PLT entry. */
if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
insn = sparc_fetch_instruction (pc);
/* Recognize a SETHI insn and record its destination. */
if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
{
dest = X_RD (insn);
offset += 4;
insn = sparc_fetch_instruction (pc + 4);
}
/* Allow for an arithmetic operation on DEST or %g1. */
if (X_OP (insn) == 2 && X_I (insn)
&& (X_RD (insn) == 1 || X_RD (insn) == dest))
{
offset += 4;
insn = sparc_fetch_instruction (pc + 8);
}
/* Check for the SAVE instruction that sets up the frame. */
if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
{
cache->frameless_p = 0;
return pc + offset + 4;
}
return pc;
}