/* * sends a pipeline command operation to the controller. See the Denali NAND * controller's user guide for more information (section 4.2.3.6). */ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en, bool transfer_spare, int access_type, int op) { uint32_t addr, cmd, irq_status; static uint32_t page_count = 1; setup_ecc_for_xfer(denali, ecc_en, transfer_spare); clear_interrupts(denali); addr = BANK(denali->flash_bank) | denali->page; /* setup the acccess type */ cmd = MODE_10 | addr; index_addr(denali, cmd, access_type); /* setup the pipeline command */ index_addr(denali, cmd, 0x2000 | op | page_count); cmd = MODE_01 | addr; writel(cmd, denali->flash_mem + INDEX_CTRL_REG); if (op == DENALI_READ) { /* wait for command to be accepted */ irq_status = wait_for_irq(denali, INTR_STATUS__LOAD_COMP); if (irq_status == 0) return -EIO; } return 0; }
static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) { uint16_t status = PASS; uint32_t id_bytes[8], addr; uint8_t maf_id, device_id; int i; /* * Use read id method to get device ID and other params. * For some NAND chips, controller can't report the correct * device ID by reading from DEVICE_ID register */ addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, 0x90); index_addr(denali, addr | 1, 0); for (i = 0; i < 8; i++) index_addr_read_data(denali, addr | 2, &id_bytes[i]); maf_id = id_bytes[0]; device_id = id_bytes[1]; if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ if (FAIL == get_onfi_nand_para(denali)) return FAIL; } else if (maf_id == 0xEC) { /* Samsung NAND */ get_samsung_nand_para(denali, device_id); } else if (maf_id == 0x98) { /* Toshiba NAND */ get_toshiba_nand_para(denali); } else if (maf_id == 0xAD) { /* Hynix NAND */ get_hynix_nand_para(denali, device_id); } dev_info(denali->dev, "Dump timing register values:\n" "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", ioread32(denali->flash_reg + ACC_CLKS), ioread32(denali->flash_reg + RE_2_WE), ioread32(denali->flash_reg + RE_2_RE), ioread32(denali->flash_reg + WE_2_RE), ioread32(denali->flash_reg + ADDR_2_DATA), ioread32(denali->flash_reg + RDWR_EN_LO_CNT), ioread32(denali->flash_reg + RDWR_EN_HI_CNT), ioread32(denali->flash_reg + CS_SETUP_CNT)); find_valid_banks(denali); detect_partition_feature(denali); /* * If the user specified to override the default timings * with a specific ONFI mode, we apply those changes here. */ if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) nand_onfi_timing_set(denali, onfi_timing_mode); return status; }
static uint16_t denali_nand_timing_set(struct denali_nand_info *denali) { uint16_t status = PASS; uint32_t id_bytes[5], addr; uint8_t i, maf_id, device_id; dev_dbg(denali->dev, "%s, Line %d, Function: %s\n", __FILE__, __LINE__, __func__); addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); index_addr(denali, (uint32_t)addr | 0, 0x90); index_addr(denali, (uint32_t)addr | 1, 0); for (i = 0; i < 5; i++) index_addr_read_data(denali, addr | 2, &id_bytes[i]); maf_id = id_bytes[0]; device_id = id_bytes[1]; if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { if (FAIL == get_onfi_nand_para(denali)) return FAIL; } else if (maf_id == 0xEC) { get_samsung_nand_para(denali, device_id); } else if (maf_id == 0x98) { get_toshiba_nand_para(denali); } else if (maf_id == 0xAD) { get_hynix_nand_para(denali, device_id); } dev_info(denali->dev, "Dump timing register values:" "acc_clks: %d, re_2_we: %d, re_2_re: %d\n" "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n" "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n", ioread32(denali->flash_reg + ACC_CLKS), ioread32(denali->flash_reg + RE_2_WE), ioread32(denali->flash_reg + RE_2_RE), ioread32(denali->flash_reg + WE_2_RE), ioread32(denali->flash_reg + ADDR_2_DATA), ioread32(denali->flash_reg + RDWR_EN_LO_CNT), ioread32(denali->flash_reg + RDWR_EN_HI_CNT), ioread32(denali->flash_reg + CS_SETUP_CNT)); find_valid_banks(denali); detect_partition_feature(denali); if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) nand_onfi_timing_set(denali, onfi_timing_mode); return status; }
/* reads OOB data from the device */ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t irq_mask = INTR_STATUS__LOAD_COMP, irq_status = 0, addr = 0x0, cmd = 0x0; denali->page = page; if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, DENALI_READ) == PASS) { read_data_from_flash_mem(denali, buf, mtd->oobsize); /* wait for command to be accepted * can always use status0 bit as the mask is identical for each * bank. */ irq_status = wait_for_irq(denali, irq_mask); if (irq_status == 0) dev_err(denali->dev, "page on OOB timeout %d\n", denali->page); /* We set the device back to MAIN_ACCESS here as I observed * instability with the controller if you do a block erase * and the last transaction was a SPARE_ACCESS. Block erase * is reliable (according to the MTD test infrastructure) * if you are in MAIN_ACCESS. */ addr = BANK(denali->flash_bank) | denali->page; cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); } }
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t addr, id; int i; switch (cmd) { case NAND_CMD_PAGEPROG: break; case NAND_CMD_STATUS: read_status(denali); break; case NAND_CMD_READID: case NAND_CMD_PARAM: reset_buf(denali); /*sometimes ManufactureId read from register is not right * e.g. some of Micron MT29F32G08QAA MLC NAND chips * So here we send READID cmd to NAND insteand * */ addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); index_addr(denali, (uint32_t)addr | 0, 0x90); index_addr(denali, (uint32_t)addr | 1, 0); for (i = 0; i < 5; i++) { index_addr_read_data(denali, (uint32_t)addr | 2, &id); write_byte_to_buf(denali, id); } break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: denali->page = page; break; case NAND_CMD_RESET: reset_bank(denali); break; case NAND_CMD_READOOB: /* TODO: Read OOB data */ break; default: printk(KERN_ERR ": unsupported command" " received 0x%x\n", cmd); break; } }
static void denali_mode_main_spare_access(struct denali_nand_info *denali) { uint32_t addr, cmd; addr = BANK(denali->flash_bank) | denali->page; cmd = MODE_10 | addr; index_addr(denali, cmd, MAIN_SPARE_ACCESS); }
static uint32_t denali_nand_timing_set(struct denali_nand_info *denali) { uint32_t id_bytes[8], addr; uint8_t maf_id, device_id; int i; /* * Use read id method to get device ID and other params. * For some NAND chips, controller can't report the correct * device ID by reading from DEVICE_ID register */ addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, 0x90); index_addr(denali, addr | 1, 0); for (i = 0; i < 8; i++) index_addr_read_data(denali, addr | 2, &id_bytes[i]); maf_id = id_bytes[0]; device_id = id_bytes[1]; if (readl(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ if (get_onfi_nand_para(denali)) return -EIO; } else if (maf_id == 0xEC) { /* Samsung NAND */ get_samsung_nand_para(denali, device_id); } else if (maf_id == 0x98) { /* Toshiba NAND */ get_toshiba_nand_para(denali); } else if (maf_id == 0xAD) { /* Hynix NAND */ get_hynix_nand_para(denali, device_id); } find_valid_banks(denali); detect_partition_feature(denali); /* * If the user specified to override the default timings * with a specific ONFI mode, we apply those changes here. */ if (onfi_timing_mode != NAND_DEFAULT_TIMINGS) nand_onfi_timing_set(denali, onfi_timing_mode); return 0; }
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t addr, id; int i; switch (cmd) { case NAND_CMD_PAGEPROG: break; case NAND_CMD_STATUS: read_status(denali); break; case NAND_CMD_READID: case NAND_CMD_PARAM: reset_buf(denali); addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); index_addr(denali, (uint32_t)addr | 0, 0x90); index_addr(denali, (uint32_t)addr | 1, 0); for (i = 0; i < 5; i++) { index_addr_read_data(denali, (uint32_t)addr | 2, &id); write_byte_to_buf(denali, id); } break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: denali->page = page; break; case NAND_CMD_RESET: reset_bank(denali); break; case NAND_CMD_READOOB: break; default: printk(KERN_ERR ": unsupported command" " received 0x%x\n", cmd); break; } }
/* determines how many NAND chips are connected to the controller. Note for * Intel CE4100 devices we don't support more than one device. */ static void find_valid_banks(struct denali_nand_info *denali) { uint32_t id[denali->max_banks]; int i; denali->total_used_banks = 1; for (i = 0; i < denali->max_banks; i++) { index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); index_addr_read_data(denali, (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); dev_dbg(denali->dev, "Return 1st ID for bank[%d]: %x\n", i, id[i]); if (i == 0) { if (!(id[i] & 0x0ff)) break; /* WTF? */ } else { if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) denali->total_used_banks++; else break; } } if (denali->platform == INTEL_CE4100) { /* Platform limitations of the CE4100 device limit * users to a single chip solution for NAND. * Multichip support is not enabled. */ if (denali->total_used_banks != 1) { dev_err(denali->dev, "Sorry, Intel CE4100 only supports " "a single NAND device.\n"); BUG(); } } dev_dbg(denali->dev, "denali->total_used_banks: %d\n", denali->total_used_banks); }
/* setups the HW to perform the data DMA */ static void denali_setup_dma(struct denali_nand_info *denali, int op) { uint32_t mode; const int page_count = 1; uint64_t addr = (unsigned long)denali->buf.dma_buf; flush_dcache_range(addr, addr + sizeof(denali->buf.dma_buf)); /* For Denali controller that is 64 bit bus IP core */ #ifdef CONFIG_SYS_NAND_DENALI_64BIT mode = MODE_10 | BANK(denali->flash_bank) | denali->page; /* DMA is a three step process */ /* 1. setup transfer type, interrupt when complete, burst len = 64 bytes, the number of pages */ index_addr(denali, mode, 0x01002000 | (64 << 16) | op | page_count); /* 2. set memory low address bits 31:0 */ index_addr(denali, mode, addr); /* 3. set memory high address bits 64:32 */ index_addr(denali, mode, addr >> 32); #else mode = MODE_10 | BANK(denali->flash_bank); /* DMA is a four step process */ /* 1. setup transfer type and # of pages */ index_addr(denali, mode | denali->page, 0x2000 | op | page_count); /* 2. set memory high address bits 23:8 */ index_addr(denali, mode | (((addr >> 16) & 0xffff) << 8), 0x2200); /* 3. set memory low address bits 23:8 */ index_addr(denali, mode | ((addr & 0xffff) << 8), 0x2300); /* 4. interrupt when complete, burst len = 64 bytes */ index_addr(denali, mode | 0x14000, 0x2400); #endif }
static void denali_setup_dma(struct denali_nand_info *denali, int op) { uint32_t mode = 0x0; const int page_count = 1; dma_addr_t addr = denali->buf.dma_buf; mode = MODE_10 | BANK(denali->flash_bank); index_addr(denali, mode | denali->page, 0x2000 | op | page_count); index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); index_addr(denali, mode | 0x14000, 0x2400); }
/* * determines how many NAND chips are connected to the controller. Note for * Intel CE4100 devices we don't support more than one device. */ static void find_valid_banks(struct denali_nand_info *denali) { uint32_t id[denali->max_banks]; int i; denali->total_used_banks = 1; for (i = 0; i < denali->max_banks; i++) { index_addr(denali, MODE_11 | (i << 24) | 0, 0x90); index_addr(denali, MODE_11 | (i << 24) | 1, 0); index_addr_read_data(denali, MODE_11 | (i << 24) | 2, &id[i]); if (i == 0) { if (!(id[i] & 0x0ff)) break; } else { if ((id[i] & 0x0ff) == (id[0] & 0x0ff)) denali->total_used_banks++; else break; } } }
/* setups the HW to perform the data DMA */ static void denali_setup_dma(struct denali_nand_info *denali, int op) { uint32_t mode = 0x0; const int page_count = 1; dma_addr_t addr = denali->buf.dma_buf; mode = MODE_10 | BANK(denali->flash_bank); /* DMA is a four step process */ /* 1. setup transfer type and # of pages */ index_addr(denali, mode | denali->page, 0x2000 | op | page_count); /* 2. set memory high address bits 23:8 */ index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200); /* 3. set memory low address bits 23:8 */ index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300); /* 4. interrupt when complete, burst len = 64 bytes*/ index_addr(denali, mode | 0x14000, 0x2400); }
static int denali_erase(struct mtd_info *mtd, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t cmd, irq_status; clear_interrupts(denali); /* setup page read request for access type */ cmd = MODE_10 | BANK(denali->flash_bank) | page; index_addr(denali, cmd, 0x1); /* wait for erase to complete or failure to occur */ irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | INTR_STATUS__ERASE_FAIL); return irq_status & INTR_STATUS__ERASE_FAIL ? NAND_STATUS_FAIL : PASS; }
static void denali_erase(struct mtd_info *mtd, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t cmd = 0x0, irq_status = 0; clear_interrupts(denali); cmd = MODE_10 | BANK(denali->flash_bank) | page; index_addr(denali, (uint32_t)cmd, 0x1); irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | INTR_STATUS__ERASE_FAIL); denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ? NAND_STATUS_FAIL : PASS; }
static void denali_erase(struct mtd_info *mtd, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t cmd, irq_status; /* clear interrupts */ clear_interrupts(denali); /* setup page read request for access type */ cmd = MODE_10 | BANK(denali->flash_bank) | page; index_addr(denali, cmd, 0x1); /* wait for erase to complete or failure to occur */ irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP | INTR_STATUS__ERASE_FAIL); if (irq_status & INTR_STATUS__ERASE_FAIL || irq_status & INTR_STATUS__LOCKED_BLK) denali->status = NAND_STATUS_FAIL; else denali->status = 0; }
static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t irq_mask = INTR_STATUS__LOAD_COMP, irq_status = 0, addr = 0x0, cmd = 0x0; denali->page = page; if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS, DENALI_READ) == PASS) { read_data_from_flash_mem(denali, buf, mtd->oobsize); irq_status = wait_for_irq(denali, irq_mask); if (irq_status == 0) dev_err(denali->dev, "page on OOB timeout %d\n", denali->page); addr = BANK(denali->flash_bank) | denali->page; cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); } }
/* writes OOB data to the device */ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t irq_status; uint32_t irq_mask = INTR_STATUS__PROGRAM_COMP | INTR_STATUS__PROGRAM_FAIL; int status = 0; denali->page = page; if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS, DENALI_WRITE) == PASS) { write_data_to_flash_mem(denali, buf, mtd->oobsize); /* wait for operation to complete */ irq_status = wait_for_irq(denali, irq_mask); if (irq_status == 0) { dev_err(denali->dev, "OOB write failed\n"); status = -EIO; } /* set the device back to MAIN_ACCESS */ { uint32_t addr; uint32_t cmd; addr = BANK(denali->flash_bank) | denali->page; cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, MAIN_ACCESS); } } else { dev_err(denali->dev, "unable to send pipeline command\n"); status = -EIO; } return status; }
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t addr, id; uint32_t pages_per_block; uint32_t block; int i; switch (cmd) { case NAND_CMD_PAGEPROG: break; case NAND_CMD_STATUS: read_status(denali); break; case NAND_CMD_READID: reset_buf(denali); /* * sometimes ManufactureId read from register is not right * e.g. some of Micron MT29F32G08QAA MLC NAND chips * So here we send READID cmd to NAND insteand */ addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, 0x90); index_addr(denali, addr | 1, col); for (i = 0; i < 8; i++) { index_addr_read_data(denali, addr | 2, &id); write_byte_to_buf(denali, id); } break; case NAND_CMD_PARAM: reset_buf(denali); /* turn on R/B interrupt */ denali_set_intr_modes(denali, false); denali_irq_mask = DENALI_IRQ_ALL | INTR_STATUS__INT_ACT; clear_interrupts(denali); denali_irq_enable(denali, denali_irq_mask); denali_set_intr_modes(denali, true); addr = (uint32_t)MODE_11 | BANK(denali->flash_bank); index_addr(denali, (uint32_t)addr | 0, cmd); index_addr(denali, (uint32_t)addr | 1, col & 0xFF); /* Wait tR time... */ udelay(25); /* And then wait for R/B interrupt */ wait_for_irq(denali, INTR_STATUS__INT_ACT); /* turn off R/B interrupt now */ denali_irq_mask = DENALI_IRQ_ALL; denali_set_intr_modes(denali, false); denali_irq_enable(denali, denali_irq_mask); denali_set_intr_modes(denali, true); for (i = 0; i < 256; i++) { index_addr_read_data(denali, (uint32_t)addr | 2, &id); write_byte_to_buf(denali, id); } break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: denali->page = page; break; case NAND_CMD_RESET: reset_bank(denali); break; case NAND_CMD_READOOB: /* TODO: Read OOB data */ break; case NAND_CMD_UNLOCK1: pages_per_block = mtd->erasesize / mtd->writesize; block = page / pages_per_block; addr = (uint32_t)MODE_10 | (block * pages_per_block); index_addr(denali, addr, 0x10); break; case NAND_CMD_UNLOCK2: pages_per_block = mtd->erasesize / mtd->writesize; block = (page+pages_per_block-1) / pages_per_block; addr = (uint32_t)MODE_10 | (block * pages_per_block); index_addr(denali, addr, 0x11); break; case NAND_CMD_ERASE1: case NAND_CMD_ERASE2: addr = MODE_10 | BANK(denali->flash_bank) | page; index_addr(denali, addr, 0x1); break; default: pr_err(": unsupported command received 0x%x\n", cmd); break; } }
/* sends a pipeline command operation to the controller. See the Denali NAND * controller's user guide for more information (section 4.2.3.6). */ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en, bool transfer_spare, int access_type, int op) { int status = PASS; uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, irq_mask = 0; if (op == DENALI_READ) irq_mask = INTR_STATUS__LOAD_COMP; else if (op == DENALI_WRITE) irq_mask = 0; else BUG(); setup_ecc_for_xfer(denali, ecc_en, transfer_spare); /* clear interrupts */ clear_interrupts(denali); addr = BANK(denali->flash_bank) | denali->page; if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { /* read spare area */ cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, access_type); cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } else if (op == DENALI_READ) { /* setup page read request for access type */ cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, access_type); /* page 33 of the NAND controller spec indicates we should not use the pipeline commands in Spare area only mode. So we don't. */ if (access_type == SPARE_ACCESS) { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } else { index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count); /* wait for command to be accepted * can always use status0 bit as the * mask is identical for each * bank. */ irq_status = wait_for_irq(denali, irq_mask); if (irq_status == 0) { dev_err(denali->dev, "cmd, page, addr on timeout " "(0x%x, 0x%x, 0x%x)\n", cmd, denali->page, addr); status = FAIL; } else { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } } } return status; }
int denali_init(struct denali_nand_info *denali) { int ret = 0; uint32_t val; if (denali->platform == INTEL_CE4100) { /* * Due to a silicon limitation, we can only support * ONFI timing mode 1 and below. */ if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n"); return -EINVAL; } } /* allocate a temporary buffer for nand_scan_ident() */ denali->buf.buf = kzalloc(PAGE_SIZE, GFP_DMA | GFP_KERNEL); if (!denali->buf.buf) return -ENOMEM; denali->mtd.parent = denali->dev; denali_hw_init(denali); denali_drv_init(denali); denali_set_intr_modes(denali, true); denali->mtd.name = "denali-nand"; denali->mtd.priv = &denali->nand; /* register the driver with the NAND core subsystem */ denali->nand.read_buf = denali_read_buf; denali->nand.select_chip = denali_select_chip; denali->nand.cmdfunc = denali_cmdfunc; denali->nand.read_byte = denali_read_byte; denali->nand.waitfunc = denali_waitfunc; /* * scan for NAND devices attached to the controller * this is the first stage in a two step process to register * with the nand subsystem */ if (nand_scan_ident(&denali->mtd, denali->max_banks, NULL)) { ret = -ENXIO; goto failed_req_irq; } /* allocate the right size buffer now */ kfree(denali->buf.buf); denali->buf.buf = kzalloc(denali->mtd.writesize + denali->mtd.oobsize, GFP_KERNEL); if (!denali->buf.buf) { ret = -ENOMEM; goto failed_req_irq; } /* * support for multi nand * MTD known nothing about multi nand, so we should tell it * the real pagesize and anything necessery */ denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED); denali->nand.chipsize <<= (denali->devnum - 1); denali->nand.page_shift += (denali->devnum - 1); denali->nand.pagemask = (denali->nand.chipsize >> denali->nand.page_shift) - 1; denali->nand.bbt_erase_shift += (denali->devnum - 1); denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift; denali->nand.chip_shift += (denali->devnum - 1); denali->mtd.writesize <<= (denali->devnum - 1); denali->mtd.oobsize <<= (denali->devnum - 1); denali->mtd.erasesize <<= (denali->devnum - 1); denali->mtd.size = denali->nand.numchips * denali->nand.chipsize; denali->bbtskipbytes *= denali->devnum; /* * second stage of the NAND scan * this stage requires information regarding ECC and * bad block management. */ /* Bad block table description is set by nand framework, see nand_bbt.c */ denali->nand.bbt_options |= NAND_BBT_USE_FLASH; denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME; if (denali->have_hw_ecc_fixup) { /* We have OOB support, so allow scan of BBT and leave the OOB alone */ denali->nand.bbt_options |= NAND_BBT_NO_OOB; } else { /* skip the scan for now until we have OOB read and write support */ denali->nand.options |= NAND_SKIP_BBTSCAN; } /* no subpage writes on denali */ denali->nand.options |= NAND_NO_SUBPAGE_WRITE; /* * Denali Controller only support 15bit and 8bit ECC in MRST, * so just let controller do 15bit ECC for MLC and 8bit ECC for * SLC if possible. * */ if (!nand_is_slc(&denali->nand) && (denali->mtd.oobsize > (denali->bbtskipbytes + ECC_15BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE)))) { /* if MLC OOB size is large enough, use 15bit ECC*/ denali->nand.ecc.strength = 15; denali->nand.ecc.layout = &nand_15bit_oob; denali->nand.ecc.bytes = ECC_15BITS; iowrite32(15, denali->flash_reg + ECC_CORRECTION); } else if (denali->mtd.oobsize < (denali->bbtskipbytes + ECC_8BITS * (denali->mtd.writesize / ECC_SECTOR_SIZE))) { pr_err("Your NAND chip OOB is not large enough to contain 8bit ECC correction codes"); goto failed_req_irq; } else { denali->nand.ecc.strength = 8; denali->nand.ecc.layout = &nand_8bit_oob; denali->nand.ecc.bytes = ECC_8BITS; iowrite32(8, denali->flash_reg + ECC_CORRECTION); } denali->nand.ecc.bytes *= denali->devnum; denali->nand.ecc.strength *= denali->devnum; denali->nand.ecc.layout->eccbytes *= denali->mtd.writesize / ECC_SECTOR_SIZE; denali->nand.ecc.layout->oobfree[0].offset = denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes; denali->nand.ecc.layout->oobfree[0].length = denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes - denali->bbtskipbytes; /* * Let driver know the total blocks number and how many blocks * contained by each nand chip. blksperchip will help driver to * know how many blocks is taken by FW. */ denali->totalblks = denali->mtd.size >> denali->nand.phys_erase_shift; denali->blksperchip = denali->totalblks / denali->nand.numchips; /* override the default read operations */ denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum; denali->nand.ecc.read_page = denali_read_page; denali->nand.ecc.read_page_raw = denali_read_page_raw; denali->nand.ecc.write_page = denali_write_page; denali->nand.ecc.write_page_raw = denali_write_page_raw; denali->nand.ecc.read_oob = denali_read_oob; denali->nand.ecc.write_oob = denali_write_oob; /* Occasionally the controller is in SPARE or MAIN+SPARE mode upon startup, and we want it to be MAIN only */ val = ioread32(denali->flash_reg + TRANSFER_MODE); if (val != 0) { int i; dev_dbg(denali->dev, "setting TRANSFER_MODE (%08x) back to MAIN only\n", val); /* put all banks in MAIN mode, no SPARE */ iowrite32(0, denali->flash_reg + TRANSFER_SPARE_REG); for (i = 0; i < 4; i++) index_addr(denali, MODE_10 | BANK(i) | 1, MAIN_ACCESS); } if (nand_scan_tail(&denali->mtd)) { ret = -ENXIO; goto failed_req_irq; } return add_mtd_nand_device(&denali->mtd, "nand"); failed_req_irq: denali_irq_cleanup(denali->irq, denali); return ret; }
static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en, bool transfer_spare, int access_type, int op) { int status = PASS; uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, irq_mask = 0; if (op == DENALI_READ) irq_mask = INTR_STATUS__LOAD_COMP; else if (op == DENALI_WRITE) irq_mask = 0; else BUG(); setup_ecc_for_xfer(denali, ecc_en, transfer_spare); clear_interrupts(denali); addr = BANK(denali->flash_bank) | denali->page; if (op == DENALI_WRITE && access_type != SPARE_ACCESS) { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) { cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, access_type); cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } else if (op == DENALI_READ) { cmd = MODE_10 | addr; index_addr(denali, (uint32_t)cmd, access_type); if (access_type == SPARE_ACCESS) { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } else { index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count); irq_status = wait_for_irq(denali, irq_mask); if (irq_status == 0) { dev_err(denali->dev, "cmd, page, addr on timeout " "(0x%x, 0x%x, 0x%x)\n", cmd, denali->page, addr); status = FAIL; } else { cmd = MODE_01 | addr; iowrite32(cmd, denali->flash_mem); } } } return status; }
static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, int page) { struct denali_nand_info *denali = mtd_to_denali(mtd); uint32_t addr; switch (cmd) { case NAND_CMD_PAGEPROG: break; case NAND_CMD_STATUS: addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); break; case NAND_CMD_READID: case NAND_CMD_PARAM: reset_buf(denali); /* * sometimes ManufactureId read from register is not right * e.g. some of Micron MT29F32G08QAA MLC NAND chips * So here we send READID cmd to NAND insteand */ addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); index_addr(denali, addr | 1, col & 0xFF); if (cmd == NAND_CMD_PARAM) udelay(50); break; case NAND_CMD_RNDOUT: addr = MODE_11 | BANK(denali->flash_bank); index_addr(denali, addr | 0, cmd); index_addr(denali, addr | 1, col & 0xFF); index_addr(denali, addr | 1, col >> 8); index_addr(denali, addr | 0, NAND_CMD_RNDOUTSTART); break; case NAND_CMD_READ0: case NAND_CMD_SEQIN: denali->page = page; break; case NAND_CMD_RESET: reset_bank(denali); break; case NAND_CMD_READOOB: /* TODO: Read OOB data */ break; case NAND_CMD_ERASE1: /* * supporting block erase only, not multiblock erase as * it will cross plane and software need complex calculation * to identify the block count for the cross plane */ denali_erase(mtd, page); break; case NAND_CMD_ERASE2: /* nothing to do here as it was done during NAND_CMD_ERASE1 */ break; case NAND_CMD_UNLOCK1: addr = MODE_10 | BANK(denali->flash_bank) | page; index_addr(denali, addr | 0, DENALI_UNLOCK_START); break; case NAND_CMD_UNLOCK2: addr = MODE_10 | BANK(denali->flash_bank) | page; index_addr(denali, addr | 0, DENALI_UNLOCK_END); break; case NAND_CMD_LOCK: addr = MODE_10 | BANK(denali->flash_bank); index_addr(denali, addr | 0, DENALI_LOCK); break; default: printf(": unsupported command received 0x%x\n", cmd); break; } }