void build_route(int width_fac) {
clock_t begin, end;
boolean success;
t_graph_type graph_type;
short wire_to_ipin_switch, global_route_switch, delayless_switch;
int Warnings;
enum e_base_cost_type base_cost_type;
graph_type = GRAPH_UNIDIR;
base_cost_type = DELAY_NORMALIZED;
init_chan(width_fac, Arch.Chans);
begin = clock();
/* Set up the routing resource graph defined by this FPGA architecture. */
build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid,
chan_width_x[0], NULL, Arch.SBType, Arch.Fs, Arch.num_segments,
RoutingArch->num_switch, Arch.Segments,
RoutingArch->global_route_switch, RoutingArch->delayless_switch,
*Timing, RoutingArch->wire_to_ipin_switch, base_cost_type,
&Warnings);
end = clock();
#ifdef CLOCKS_PER_SEC
printf("build rr_graph took %g seconds\n",
(float) (end - begin) / CLOCKS_PER_SEC);
#else
printf("build rr_graph took %g seconds\n",
(float) (end - begin) / CLK_PER_SEC);
#endif
}
int decimate(FIR_filter *FIR, int dec_fac, double *yi, int ni, double *yo, int *no)
{
int i,j,N;
double sample_value ;
channel chan ;
if ( dec_fac == 1 ) return 0;
init_chan(&chan,FIR);
j = 0 ;
N = FIR->n1+FIR->n2 ;
for(i=FIR->n2;i<N;i++)
chan.segment[i]=yi[i-FIR->n2];
for(i=FIR->n1;i<ni+FIR->n1;i++)
{
if (i<ni)
sample_value = yi[i] ;
else
sample_value = 0. ;
push_back(chan.segment,N,sample_value);
if(chan.counter >= 0 && chan.counter % dec_fac == 0)
{
yo[j] = dot(FIR->coeffs,N,chan.segment,N);
chan.counter = 0;
j++;
}
++(chan.counter);
}
(*no)=j;
return 0;
}
static void
setup_chan_width(struct s_router_opts router_opts,
t_chan_width_dist chan_width_dist)
{
/*we give plenty of tracks, this increases routability for the */
/*lookup table generation */
int width_fac, i, max_pins_per_clb;
max_pins_per_clb = 0;
for(i = 0; i < num_types; i++)
{
max_pins_per_clb =
max(max_pins_per_clb, type_descriptors[i].num_pins);
}
if(router_opts.fixed_channel_width == NO_FIXED_CHANNEL_WIDTH)
width_fac = 4 * max_pins_per_clb; /*this is 2x the value that binary search starts */
/*this should be enough to allow most pins to */
/*connect to tracks in the architecture */
else
width_fac = router_opts.fixed_channel_width;
init_chan(width_fac, chan_width_dist);
}
boolean try_route (int width_fac, struct s_router_opts router_opts, struct
s_det_routing_arch det_routing_arch, t_segment_inf *segment_inf,
t_timing_inf timing_inf, float **net_slack, float **net_delay,
t_chan_width_dist chan_width_dist, t_ivec **clb_opins_used_locally) {
/* Attempts a routing via an iterated maze router algorithm. Width_fac *
* specifies the relative width of the channels, while the members of *
* router_opts determine the value of the costs assigned to routing *
* resource node, etc. det_routing_arch describes the detailed routing *
* architecture (connection and switch boxes) of the FPGA; it is used *
* only if a DETAILED routing has been selected. */
boolean success;
printf("\nAttempting routing with a width factor (usually maximum channel ");
printf("width) of %d.\n",width_fac);
/* Set the channel widths */
init_chan (width_fac, chan_width_dist);
/* Free any old routing graph, if one exists. */
free_rr_graph ();
/* Set up the routing resource graph defined by this FPGA architecture. */
build_rr_graph (router_opts.route_type, det_routing_arch, segment_inf,
timing_inf, router_opts.base_cost_type);
/* Allocate and load some additional rr_graph information needed only by *
* the router. */
alloc_and_load_rr_node_route_structs ();
init_route_structs (router_opts.bb_factor);
if (router_opts.router_algorithm == BREADTH_FIRST)
success = try_breadth_first_route (router_opts, clb_opins_used_locally);
else /* TIMING_DRIVEN route */
success = try_timing_driven_route (router_opts, net_slack, net_delay,
clb_opins_used_locally);
free_rr_node_route_structs ();
return (success);
}
boolean
try_route(int width_fac,
struct s_router_opts router_opts,
struct s_det_routing_arch det_routing_arch,
t_segment_inf * segment_inf,
t_timing_inf timing_inf,
float **net_slack,
float **net_delay,
t_chan_width_dist chan_width_dist,
t_ivec ** fb_opins_used_locally,
t_mst_edge ** mst,
boolean * Fc_clipped)
{
/* Attempts a routing via an iterated maze router algorithm. Width_fac *
* specifies the relative width of the channels, while the members of *
* router_opts determine the value of the costs assigned to routing *
* resource node, etc. det_routing_arch describes the detailed routing *
* architecture (connection and switch boxes) of the FPGA; it is used *
* only if a DETAILED routing has been selected. */
int tmp;
boolean success;
t_graph_type graph_type;
if(router_opts.route_type == GLOBAL) {
graph_type = GRAPH_GLOBAL;
} else {
graph_type = (det_routing_arch.directionality ==
BI_DIRECTIONAL ? GRAPH_BIDIR : GRAPH_UNIDIR);
}
/* Set the channel widths */
init_chan(width_fac, chan_width_dist);
/* Free any old routing graph, if one exists. */
free_rr_graph();
/* Set up the routing resource graph defined by this FPGA architecture. */
build_rr_graph(graph_type,
num_types, type_descriptors, nx, ny, grid,
chan_width_x[0], NULL,
det_routing_arch.switch_block_type, det_routing_arch.Fs,
det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf,
det_routing_arch.global_route_switch,
det_routing_arch.delayless_switch, timing_inf,
det_routing_arch.wire_to_ipin_switch,
router_opts.base_cost_type, &tmp);
/* Allocate and load some additional rr_graph information needed only by *
* the router. */
alloc_and_load_rr_node_route_structs();
init_route_structs(router_opts.bb_factor);
if(router_opts.router_algorithm == BREADTH_FIRST)
{
printf("Confirming Router Algorithm: BREADTH_FIRST.\n");
success =
try_breadth_first_route(router_opts, fb_opins_used_locally,
width_fac);
}
else if(router_opts.router_algorithm == TIMING_DRIVEN)
{ /* TIMING_DRIVEN route */
printf("Confirming Router Algorithm: TIMING_DRIVEN.\n");
assert(router_opts.route_type != GLOBAL);
success =
try_timing_driven_route(router_opts, net_slack, net_delay,
fb_opins_used_locally);
}
else
{ /* Directed Search Routability Driven */
printf("Confirming Router Algorithm: DIRECTED_SEARCH.\n");
success =
try_directed_search_route(router_opts, fb_opins_used_locally,
width_fac, mst);
}
free_rr_node_route_structs();
return (success);
}
