/*! \brief Initializes the MCU system clocks.
*/
static void init_sys_clocks(void)
{
// Switch to OSC0 to speed up the booting
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Start oscillator1
pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
//
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set PLL0 (fed from OSC1 = 11.2896 MHz) to 112.896 MHz
// We use OSC1 since we need a correct master clock for the SSC module to generate
// the correct sample rate
pm_pll_setup(&AVR32_PM, 0, // pll.
SYS_CLOCK_PLL_MUL-1, // mul.
1, // div.
1, // osc.
16); // lockcount.
// Set PLL operating range and divider (fpll = fvco/2)
// -> PLL0 output = 62.0928 MHz
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL0 and wait for the lock
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
// Set all peripheral clocks torun at master clock rate
pm_cksel(&AVR32_PM,
0, // pbadiv.
0, // pbasel.
0, // pbbdiv.
0, // pbbsel.
0, // hsbdiv.
0); // hsbsel.
// Set one waitstate for the flash
flashc_set_wait_state(1);
// Switch to PLL0 as the master clock
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
#if (defined USB_RESYNC_METHOD) && (USB_RESYNC_METHOD == USB_RESYNC_METHOD_EXT_CLOCK_SYNTHESIZER)
// Holds frequencies parameters
g_fcpu_hz = g_fhsb_hz = g_fpba_hz = g_fpbb_hz = FMCK_HZ(11289600);
#endif
#if (defined __GNUC__) && (defined __AVR32__)
// Give the used PBA clock frequency to Newlib, so it can work properly.
set_cpu_hz(FPBA_HZ);
#endif
init_usb_clock();
init_codec_gclk();
}
/*! \brief Initializes the MCU system clocks.
*/
void init_sys_clocks(void)
{
// Switch to OSC0 to speed up the booting
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Start oscillator1
pm_enable_osc1_crystal(&AVR32_PM, FOSC1);
//
pm_enable_clk1(&AVR32_PM, OSC1_STARTUP);
// Set PLL0 (fed from OSC1 = 11.2896 MHz) to 124.1856 MHz
// We use OSC1 since we need a correct master clock for the SSC module to generate
// the correct sample rate
pm_pll_setup(&AVR32_PM, 0, // pll.
10, // mul.
1, // div.
1, // osc.
16); // lockcount.
// Set PLL operating range and divider (fpll = fvco/2)
// -> PLL0 output = 62.0928 MHz
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// start PLL0 and wait for the lock
pm_pll_enable(&AVR32_PM, 0);
pm_wait_for_pll0_locked(&AVR32_PM);
// Set all peripheral clocks to run at master clock rate
pm_cksel(&AVR32_PM,
0, // pbadiv.
0, // pbasel.
0, // pbbdiv.
0, // pbbsel.
0, // hsbdiv.
0); // hsbsel.
// Set one waitstate for the flash
flashc_set_wait_state(1);
// Switch to PLL0 as the master clock
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
init_usb_clock();
init_codec_gclk();
}
