int board_early_init_f (void)
{
out32 (REG (CPC0, RSTR), 0xC0000000);
iobarrier_rw ();
out32 (REG (CPC0, RSTR), 0xF0000000);
iobarrier_rw ();
out32 (REG (CPC0, UCTL), 0x00F80000);
out32 (REG (CPC0, SIOC0), 0x30000000);
out32 (REG (CPC0, ABCNTL), 0x00000000);
out32 (REG (CPC0, SESR), 0x00000000);
out32 (REG (CPC0, SEAR), 0x00000000);
/* Detect IBM Avignon CPC710 Revision */
if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P)
out32 (REG (CPC0, PGCHP), 0xA0000040);
else
out32 (REG (CPC0, PGCHP), 0x80800040);
out32 (REG (CPC0, ATAS), 0x709C2508);
iobarrier_rw ();
return 0;
}
/*
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile ulong addr = info->start[0];
ulong start;
int i;
flash_to_xd();
/* Check if Flash is (sufficiently) erased */
if ((in32(dest) & data) != data) {
flash_to_mem();
return (2);
}
/* write each byte out */
for (i = 0; i < 4; i++) {
char *data_ch = (char *)&data;
int flag = disable_interrupts();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0xA0);
iobarrier_rw();
out8(dest+i, data_ch[i]);
iobarrier_rw();
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
flash_reset (addr);
flash_to_mem();
return (1);
}
iobarrier_rw();
}
}
flash_reset (addr);
flash_to_mem();
return (0);
}
/*
* Reset bank to read mode
*/
static void flash_reset (ulong addr)
{
flash_to_xd();
out8(addr, 0xF0); /* reset bank */
iobarrier_rw();
flash_to_mem();
}
static void amiga_serial_putc(char c)
{
custom.serdat = (unsigned char)c | 0x100;
iobarrier_rw ();
while (!(custom.serdatr & 0x2000))
;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
out32 (REG (CPC0, SPOR), 0);
iobarrier_rw ();
while (1);
/* notreached */
return (-1);
}
void pcippc2_cpci3264_init (void)
{
pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0);
if (bdf == -1)
{
puts("Unable to find FPGA !\n");
hang();
}
if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000)
/* 32-bits Compact PCI bus - LSB bit */
{
iobarrier_rw();
out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */
iobarrier_rw();
}
}
/*
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile u32 addr = info->start[0];
ulong start;
int flag, i;
/* Check if Flash is (sufficiently) erased */
if ((in32(dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* first, perform an unlock bypass command to speed up flash writes */
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0x20);
iobarrier_rw();
/* write each byte out */
for (i = 0; i < 4; i++) {
char *data_ch = (char *)&data;
out8(addr, 0xA0);
iobarrier_rw();
out8(dest+i, data_ch[i]);
iobarrier_rw();
udelay(10); /* XXX */
}
/* we're done, now do an unlock bypass reset */
out8(addr, 0x90);
iobarrier_rw();
out8(addr, 0x00);
iobarrier_rw();
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
iobarrier_rw();
}
flash_reset (addr);
return (0);
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile ulong addr = info->start[0];
int flag, prot, sect, l_sect;
ulong start, now, last;
flash_to_xd();
if (s_first < 0 || s_first > s_last) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
flash_to_mem();
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
flash_to_mem();
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0x80);
iobarrier_rw();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = info->start[sect];
out8(addr, 0x30);
iobarrier_rw();
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = info->start[l_sect];
DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
while ((in8(addr) & 0x80) != 0x80) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
flash_reset (info->start[0]);
flash_to_mem();
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
iobarrier_rw();
}
DONE:
/* reset to read mode */
flash_reset (info->start[0]);
flash_to_mem();
printf (" done\n");
return 0;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (ulong addr, flash_info_t *info)
{
short i;
uchar value;
uchar *x = (uchar *)addr;
flash_to_xd();
/* Write auto select command: read Manufacturer ID */
x[0x0555] = 0xAA;
__asm volatile ("sync\n eieio");
x[0x02AA] = 0x55;
__asm volatile ("sync\n eieio");
x[0x0555] = 0x90;
__asm volatile ("sync\n eieio");
value = x[0];
__asm volatile ("sync\n eieio");
DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value);
switch (value | (value << 16)) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
flash_reset (addr);
return 0;
}
value = x[1];
__asm volatile ("sync\n eieio");
DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value);
switch (value) {
case AMD_ID_F040B:
DEBUGF("Am29F040B\n");
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break; /* => 512 kB */
case AMD_ID_LV040B:
DEBUGF("Am29LV040B\n");
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break; /* => 512 kB */
case AMD_ID_LV400T:
DEBUGF("Am29LV400T\n");
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV400B:
DEBUGF("Am29LV400B\n");
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV800T:
DEBUGF("Am29LV800T\n");
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
DEBUGF("Am29LV400B\n");
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV160T:
DEBUGF("Am29LV160T\n");
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV160B:
DEBUGF("Am29LV160B\n");
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00400000;
break; /* => 4 MB */
case AMD_ID_LV320T:
DEBUGF("Am29LV320T\n");
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
#if 0
/* Has the same ID as AMD_ID_LV320T, to be fixed */
case AMD_ID_LV320B:
DEBUGF("Am29LV320B\n");
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00800000;
break; /* => 8 MB */
#endif
case AMD_ID_LV033C:
DEBUGF("Am29LV033C\n");
info->flash_id += FLASH_AM033C;
info->sector_count = 64;
info->size = 0x01000000;
break; /* => 16Mb */
case STM_ID_F040B:
DEBUGF("M29F040B\n");
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break; /* => 512 kB */
default:
info->flash_id = FLASH_UNKNOWN;
flash_reset (addr);
flash_to_mem();
return (0); /* => no or unknown flash */
}
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
printf ("** ERROR: sector count %d > max (%d) **\n",
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
}
if (! flash_get_offsets (addr, info)) {
flash_reset (addr);
flash_to_mem();
return 0;
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
value = in8(info->start[i] + 2);
iobarrier_rw();
info->protect[i] = (value & 1) != 0;
}
/*
* Reset bank to read mode
*/
flash_reset (addr);
flash_to_mem();
return (info->size);
}
/*
* Reset bank to read mode
*/
static void flash_reset (u32 addr)
{
out8(addr, 0xF0); /* reset bank */
iobarrier_rw();
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (u32 addr, flash_info_t *info)
{
volatile uchar value;
#if 0
int i;
#endif
/* Write auto select command: read Manufacturer ID */
out8(addr + 0x0555, 0xAA);
iobarrier_rw();
udelay(10);
out8(addr + 0x02AA, 0x55);
iobarrier_rw();
udelay(10);
out8(addr + 0x0555, 0x90);
iobarrier_rw();
udelay(10);
value = in8(addr);
iobarrier_rw();
udelay(10);
switch (value | (value << 16)) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
flash_reset (addr);
return 0;
}
value = in8(addr + 1); /* device ID */
iobarrier_rw();
switch (value) {
case AMD_ID_LV033C:
info->flash_id += FLASH_AM033C;
info->size = hwc_flash_size();
if (info->size > CFG_MAX_FLASH_SIZE) {
printf("U-Boot supports only %d MB\n",
CFG_MAX_FLASH_SIZE);
info->size = CFG_MAX_FLASH_SIZE;
}
info->sector_count = info->size / 0x10000;
break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
flash_reset (addr);
return (0); /* => no or unknown flash */
}
if (!flash_get_offsets (addr, info)) {
flash_reset (addr);
return 0;
}
#if 0
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
value = in8(info->start[i] + 2);
iobarrier_rw();
info->protect[i] = (value & 1) != 0;
}
#endif
/*
* Reset bank to read mode
*/
flash_reset (addr);
return (info->size);
}
unsigned long cpc710_ram_init (void)
{
unsigned long memsize = 0;
unsigned long bank_size;
u32 mcer;
#ifndef CONFIG_SYS_RAMBOOT
/* Clear memory banks
*/
out32 (REG (SDRAM0, MCER0), 0);
out32 (REG (SDRAM0, MCER1), 0);
out32 (REG (SDRAM0, MCER2), 0);
out32 (REG (SDRAM0, MCER3), 0);
out32 (REG (SDRAM0, MCER4), 0);
out32 (REG (SDRAM0, MCER5), 0);
out32 (REG (SDRAM0, MCER6), 0);
out32 (REG (SDRAM0, MCER7), 0);
iobarrier_rw ();
/* Disable memory
*/
out32 (REG (SDRAM0, MCCR), 0x13b06000);
iobarrier_rw ();
#endif
/* Only the first memory bank is initialised now
*/
if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) {
puts ("Unsupported SDRAM type !\n");
hang ();
}
memsize += bank_size;
#ifndef CONFIG_SYS_RAMBOOT
/* Enable bank, zero start
*/
out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
iobarrier_rw ();
#endif
#ifndef CONFIG_SYS_RAMBOOT
/* Enable memory
*/
out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
/* Wait until initialisation finished
*/
while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) {
iobarrier_rw ();
}
/* Clear Memory Error Status and Address registers
*/
out32 (REG (SDRAM0, MESR), 0);
out32 (REG (SDRAM0, MEAR), 0);
iobarrier_rw ();
/* ECC is not configured now
*/
#endif
/* Memory size counter
*/
out32 (REG (CPC0, RGBAN1), memsize);
return memsize;
}
