static void cpm_interrupt_init(void)
{
immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
uint cicr;
/*
* Initialize the CPM interrupt controller.
*/
cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 |
((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
out_be32(&immr->im_cpic.cpic_cicr, cicr);
out_be32(&immr->im_cpic.cpic_cimr, 0);
/*
* Install the error handler.
*/
irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN);
/*
* Install the cpm interrupt handler
*/
irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL);
}
/* Start to initialize h/w stuff */
int udc_init (void)
{
struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_interrupt * irq = s3c24x0_get_base_interrupt();
udc_device = NULL;
/* Set and check clock control.
* We might ought to be using the clock control API to do
* this instead of fiddling with the clock registers directly
* here.
*/
clk_power->CLKCON |= (1 << 7);
/* Print banner with device revision */
printf("USB: S3C2440 USB Deviced\n");
/*
* At this point, device is ready for configuration...
*/
outl(0x00, S3C24X0_UDC_EP_INT_EN_REG);
outl(0x00, S3C24X0_UDC_USB_INT_EN_REG);
irq->INTMSK &= ~BIT_DMA2;
irq->SRCPND &= ~BIT_DMA2;
irq_install_handler(IRQ_USBD, do_usbd_irq, (void *) IRQ_USBD);
irq_install_handler(IRQ_DMA2, do_dma2, (void *) IRQ_DMA2);
return 0;
}
void irq_wait(int irq)
{
void *oldhandler;
irq_waiting[irq] = TRUE;
oldhandler = irq_routines[irq]; // save the old irq handler
irq_install_handler(irq, irq_wait_ret); // set up irq_wait_ret() as the new one
while (irq_waiting[irq] == TRUE) // wait for the irq_wait_ret function to clear the entry
{;}
irq_install_handler(irq, oldhandler); // restore the old handler
return;
}
uint32 SDPAM_INTCRegISR(SDMMC_PORT_E nSDCPort, pFunc Routine)
{
#if SDMMC_NO_PLATFORM
return TRUE;
#else
if (nSDCPort == SDC0) {
irq_install_handler(RKPLAT_IRQ_SDMMC, (interrupt_handler_t *)Routine, NULL);
} else if (nSDCPort == SDC1) {
irq_install_handler(RKPLAT_IRQ_SDIO, (interrupt_handler_t *)Routine, NULL);
} else {
irq_install_handler(RKPLAT_IRQ_EMMC, (interrupt_handler_t *)Routine, NULL);
}
return TRUE;
#endif
}
void timer_install() {
irq_install_handler ( 0, timer_handler );
T.uptime = 0;
T.ticks = 0;
clock = 0;
set_timer_interval();
}
int timer_init(void)
{
volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
timerp->tcn = 0;
timerp->trr = 0;
/* Set up TIMER 4 as clock */
timerp->tmr = DTIM_DTMR_RST_RST;
/* initialize and enable timer interrupt */
irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
timerp->tcn = 0;
timerp->trr = 1000; /* Interrupt every ms */
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
return 0;
}
int timer_init(void)
{
slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
/* disable timer */
out_be32(&timerp->cr, 0);
out_be32(&timerp->tcnt, 0);
/* clear status */
out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
/* initialize and enable timer interrupt */
irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
/* Interrupt every ms */
out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and
enable timer and interrupt */
out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
return 0;
}
int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
got_hcirq = 0;
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
irq_install_handler(IRQ0_FPGA,
(interrupt_handler_t *)fpga_interrupt,
fpga);
FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
while (!got_hcirq) {
/* Abort if ctrl-c was pressed */
if (ctrlc()) {
puts("\nAbort\n");
break;
}
}
if (got_hcirq)
printf("Got interrupt!\n");
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
irq_free_handler(IRQ0_FPGA);
return 0;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
void sunxi_dma_init(void)
{
int i;
sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
dma_int->irq_en0 = 0;
dma_int->irq_en1 = 0;
dma_int->irq_pending0 = 0xffffffff;
dma_int->irq_pending1 = 0xffffffff;
memset((void *)dma_channal_source, 0, SUNXI_DMA_MAX * sizeof(struct sunxi_dma_source_t));
for(i=0;i<SUNXI_DMA_MAX;i++)
{
dma_channal_source[i].used = 0;
dma_channal_source[i].channal = (struct sunxi_dma_channal_set_t *)(SUNXI_DMA_BASE + i * SUNXI_DMA_CHANANL_SIZE + 0x100);
dma_channal_source[i].config = (sunxi_dma_start_t *)malloc_noncache(sizeof(sunxi_dma_start_t));
}
dma_int_count = 0;
irq_install_handler(AW_IRQ_DMA, sunxi_dma_int_func, 0);
return ;
}
int timer_init(void)
{
system_ticks = 0;
irq_install_handler(0, timer_isr, NULL);
/* initialize timer 0 and 2
*
* Timer 0 is used to increment system_tick 1000 times/sec
* Timer 1 was used for DRAM refresh in early PC's
* Timer 2 is used to drive the speaker
* (to stasrt a beep: write 3 to port 0x61,
* to stop it again: write 0)
*/
outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND);
outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0);
outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0);
outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND);
outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2);
outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2);
timer_init_done = 1;
return 0;
}
/* Installs the keyboard handler into IRQ1 */
void init_keyboard()
{
kb_buf.cnt = 0;
kb_buf.head = kb_buf.tail = 0;
irq_install_handler(1, keyboard_handler);
}
/*
*******************************************************************************
* OSAL_RegISR
*
* Description:
* 注册中断服务程序
*
* Parameters:
* irqno ：input. 中断号
* flags ：input. 中断类型，默认值为0。
* Handler ：input. 中断处理程序入口，或者中断事件句柄
* pArg ：input. 参数
* DataSize ：input. 参数的长度
* prio ：input. 中断优先级
*
* Return value:
* 返回成功或者失败。
*
* note:
* 中断处理函数原型，typedef __s32 (*ISRCallback)( void *pArg)。
*
*******************************************************************************
*/
int OSAL_RegISR(__u32 IrqNo, __u32 Flags,ISRCallback Handler,void *pArg,__u32 DataSize,__u32 Prio)
{
__inf("OSAL_RegISR, irqNo=%d, Handler=0x%x, pArg=0x%x\n", IrqNo, (int)Handler, (int)pArg);
irq_install_handler(IrqNo, (interrupt_handler_t *)Handler, pArg);
return 0;
}
/* Installs the keyboard handler into IRQ1 */
void keyboard_install()
{
memset(store, '\0', strlen(store));
memset(tempch, '\0', strlen(tempch));
index = 0;
irq_install_handler(1, keyboard_handler);
}
int timer_init(void)
{
/* Register the SC520 specific timer interrupt handler */
register_timer_isr(sc520_timer_isr);
/* Install interrupt handler for GP Timer 1 */
irq_install_handler (0, timer_isr, NULL);
/* Map GP Timer 1 to Master PIC IR0 */
writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
/* Disable GP Timers 1 & 2 - Allow configuration writes */
writew(0x4000, &sc520_mmcr->gptmr1ctl);
writew(0x4000, &sc520_mmcr->gptmr2ctl);
/* Reset GP Timers 1 & 2 */
writew(0x0000, &sc520_mmcr->gptmr1cnt);
writew(0x0000, &sc520_mmcr->gptmr2cnt);
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
writew(83, &sc520_mmcr->gptmr2maxcmpa);
writew(0xc001, &sc520_mmcr->gptmr2ctl);
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
writew(100, &sc520_mmcr->gptmr1maxcmpa);
writew(0xe009, &sc520_mmcr->gptmr1ctl);
unmask_irq(0);
/* Clear the GP Timer 1 status register to get the show rolling*/
writeb(0x02, &sc520_mmcr->gptmrsta);
return 0;
}
int ps2ser_init(void)
{
int quot;
unsigned cval;
state = rs_table + CONFIG_PS2SERIAL;
quot = state->baud_base / PS2SER_BAUD;
cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
/* Set speed, enable interrupts, enable FIFO
*/
ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
ps2ser_out(UART_DLL, quot & 0xff);
ps2ser_out(UART_DLM, quot >> 8);
ps2ser_out(UART_LCR, cval);
ps2ser_out(UART_IER, UART_IER_RDI);
ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
ps2ser_out(UART_FCR,
UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
/* If we read 0xff from the LSR, there is no UART here
*/
if (ps2ser_in(UART_LSR) == 0xff) {
printf ("ps2ser.c: no UART found\n");
return -1;
}
irq_install_handler(state->irq, ps2ser_interrupt, NULL);
return 0;
}
void serial_buffered_init (void)
{
serial_puts ("Switching to interrupt driven serial input mode.\n");
buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
buf_info.rx_put = 0;
buf_info.rx_get = 0;
if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
serial_puts ("Check CTS signal present on serial port: OK.\n");
else
serial_puts ("WARNING: CTS signal not present on serial port.\n");
irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
serial_isr /*interrupt_handler_t *handler */ ,
(void *) &buf_info /*void *arg */ );
/* Enable "RX Data Available" Interrupt on UART */
out_8(ACTING_UART0_BASE + UART_IER, 0x01);
/* Set DTR active */
out_8(ACTING_UART0_BASE + UART_MCR,
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
/* Start flow by setting RTS active */
out_8(ACTING_UART0_BASE + UART_MCR,
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
}
/**************************************************************************
* int fdc_setup
* setup the fdc according the datasheet
* assuming in PS2 Mode
*/
int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG)
{
int i;
#ifdef CONFIG_AMIGAONEG3SE
irq_install_handler(6, (interrupt_handler_t *)fdc_interrupt, NULL);
i8259_unmask_irq(6);
#endif
#ifdef CFG_FDC_HW_INIT
fdc_hw_init ();
#endif
/* first, we reset the FDC via the DOR */
write_fdc_reg(FDC_DOR,0x00);
for(i=0; i<255; i++) /* then we wait some time */
udelay(500);
/* then, we clear the reset in the DOR */
pCMD->drive=drive;
select_fdc_drive(pCMD);
/* initialize the CCR */
write_fdc_reg(FDC_CCR,pFG->rate);
/* then initialize the DSR */
write_fdc_reg(FDC_DSR,pFG->rate);
if(wait_for_fdc_int()==FALSE) {
PRINTF("Time Out after writing CCR\n");
return FALSE;
}
/* now issue sense Interrupt and status command
* assuming only one drive present (drive 0) */
pCMD->dma=0; /* we don't use any dma at all */
for(i=0;i<4;i++) {
/* issue sense interrupt for all 4 possible drives */
pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT;
if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
PRINTF("Sense Interrupt for drive %d failed\n",i);
}
}
/* issue the configure command */
pCMD->drive=drive;
select_fdc_drive(pCMD);
pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE;
if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
PRINTF(" configure timeout\n");
stop_fdc_drive(pCMD);
return FALSE;
}
/* issue specify command */
pCMD->cmd[COMMAND]=FDC_CMD_SPECIFY;
if(fdc_issue_cmd(pCMD,pFG)==FALSE) {
PRINTF(" specify timeout\n");
stop_fdc_drive(pCMD);
return FALSE;
}
/* then, we clear the reset in the DOR */
/* fdc_check_drive(pCMD,pFG); */
/* write_fdc_reg(FDC_DOR,0x04); */
return TRUE;
}
int timer_init(void)
{
/* Map GP Timer 1 to Master PIC IR0 */
write_mmcr_byte (SC520_GPTMR1MAP, 0x01);
/* Disable GP Timers 1 & 2 - Allow configuration writes */
write_mmcr_word (SC520_GPTMR1CTL, 0x4000);
write_mmcr_word (SC520_GPTMR2CTL, 0x4000);
/* Reset GP Timers 1 & 2 */
write_mmcr_word (SC520_GPTMR1CNT, 0x0000);
write_mmcr_word (SC520_GPTMR2CNT, 0x0000);
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
write_mmcr_word (SC520_GPTMR2MAXCMPA, 83);
write_mmcr_word (SC520_GPTMR2CTL, 0xc001);
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
write_mmcr_word (SC520_GPTMR1MAXCMPA, 100);
write_mmcr_word (SC520_GPTMR1CTL, 0xe009);
/* Clear the GP Timers status register */
write_mmcr_byte (SC520_GPTMRSTA, 0x07);
/* Register the SC520 specific timer interrupt handler */
register_timer_isr (sc520_timer_isr);
/* Install interrupt handler for GP Timer 1 */
irq_install_handler (0, timer_isr, NULL);
unmask_irq (0);
return 0;
}
void mouse_install()
{
byte _status; //unsigned char
//Enable the auxiliary mouse device
mouse_wait(1);
outportb(0x64, 0xA8);
//Enable the interrupts
mouse_wait(1);
outportb(0x64, 0x20);
mouse_wait(0);
_status=(inportb(0x60) | 2);
mouse_wait(1);
outportb(0x64, 0x60);
mouse_wait(1);
outportb(0x60, _status);
//Tell the mouse to use default settings
mouse_write(0xF6);
mouse_read(); //Acknowledge
//Enable the mouse
mouse_write(0xF4);
mouse_read(); //Acknowledge
//Setup the mouse handler
irq_install_handler(12, mouse_handler);
}
/* Sets up the system clock by installing the timer handler
* into IRQ0 */
void timer_install()
{
/* Installs 'timer_handler' to IRQ0 */
irq_install_handler(IRQ0, &timer_handler);
set_timer_phase(freq);
print_d("Timer Installed...\n");
}
void timer_init()
{
//Install timer handler
irq_install_handler(0,timer_handler);
//Set ticks per seccond to 1000
timer_phase(1000);
}
void init_shell()
{
getCmdCount();
populateCommands();
tcputs("$>> ", COLOR_GREEN);
irq_install_handler(1, keyboard_handler);
waitCmd();
}
/* Sets up the system clock by installing the timer handler
* into IRQ0 */
void timer_install()
{
/* Installs 'timer_handler' to IRQ0 */
irq_install_handler(0, timer_handler);
/* Configure timer to 100 Hz */
timer_phase(PIT_CLOCK_HZ); /* Sys clock is 1193190 Hz */
}
// Install IRQ Handler
void timer_install()
{
irq_install_handler(0, timer_handler, "timer");
int divisor = 1193180 / _timer_hz; /* Calculate our divisor */
outb(PIT_CTRL, PIT_CMD_SET); /* Set our command byte 0x36 */
outb(PIT_PORT, divisor & PIT_MASK); /* Set low byte of divisor */
outb(PIT_PORT, (divisor >> 8) & PIT_MASK); /* Set high byte of divisor */
}
// start timer
void timer_install()
{
handler_func = 0;
handler_msec_passed = 0;
handler_counter = 0;
irq_install_handler(0, timer_handler);
timer_phase(1000); // set to ticks 1000times per second
}
/*
* rkpm wakeup gpio init
*/
void rk_pm_wakeup_gpio_init(void)
{
int irq = gpio_to_irq(RK_WAKEUP_KEY_PIN);
/* gpio pin just use to wakeup, no need isr handle */
irq_install_handler(irq, -1, NULL);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
irq_handler_enable(irq);
}
void timer_install()
{
//Set timer to 1000Hz
int divisor = 1193180 / 1000;
outportb(0x43, 0x36);
outportb(0x40, divisor & 0xFF);
outportb(0x40, divisor >> 8);
//Installs 'timer_handler' to IRQ0
irq_install_handler(0, timer_handler);
}
/**
* Install handler
*/
int kb_init(void)
{
irq_install_handler(KB_IRQ, kb_handler);
kb_buffer.push_index = kb_buffer.pop_index = 0;
IODevice* kb = io_register_device("keyboard", "Keyboard", NULL);
kb->read = kb_read;
// Attach itself to stdin
stdin = kb;
return 0;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
void sunxi_dma_init(void)
{
sunxi_dma_int_set *dma_int = (sunxi_dma_int_set *)SUNXI_DMA_BASE;
dma_int->irq_en0 = 0;
dma_int->irq_pending0 = 0xffffffff;
dma_int_count = 0;
irq_install_handler(AW_IRQ_DMA, sunxi_dma_int_func, 0);
return ;
}
int timer_init (void)
{
/* install interrupt handler for timer */
irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)×tamp);
/* setup the Timer counter value */
*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
/* enable timer irq */
*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
return 0;
}
