int target_design(ivl_design_t des)
{
const char*path = ivl_design_flag(des, "-o");
if (path == 0) {
return -1;
}
out = fopen(path, "w");
if (out == 0) {
perror(path);
return -2;
}
fprintf(out, "module %s;\n", ivl_scope_name(ivl_design_root(des)));
/* Declare all the signals. */
draw_scoped_objects(des);
/* Declare logic gates. */
draw_scope_logic(ivl_design_root(des), 0);
/* Write out processes. */
ivl_design_process(des, show_process, 0);
fprintf(out, "endmodule\n");
fclose(out);
return 0;
}
/*
* Scoped objects are the signals, reg and wire and what-not. What
* this function does is draw the objects of the scope, along with a
* fake scope context so that the hierarchical name remains
* pertinent.
*/
static void draw_scoped_objects(ivl_design_t des)
{
ivl_scope_t root = ivl_design_root(des);
unsigned cnt, idx;
cnt = ivl_scope_sigs(root);
for (idx = 0 ; idx < cnt ; idx += 1) {
ivl_signal_t sig = ivl_scope_sig(root, idx);
switch (ivl_signal_type(sig)) {
case IVL_SIT_REG:
if (ivl_signal_pins(sig) > 1)
fprintf(out, " reg [%u:0] %s;\n",
ivl_signal_pins(sig),
ivl_signal_basename(sig));
else
fprintf(out, " reg %s;\n",
ivl_signal_basename(sig));
break;
case IVL_SIT_TRI:
fprintf(out, " wire %s;\n", ivl_signal_basename(sig));
break;
default:
assert(0);
}
}
}
static void edif_show_footer(ivl_design_t des)
{
unsigned nref = 0;
struct nexus_recall*cur;
ivl_scope_t root = ivl_design_root(des);
edif_show_consts(des);
for (cur = net_list ; cur ; cur = cur->next) {
fprintf(xnf, "(net (rename N%u \"%s\") (joined %s))\n",
nref, ivl_nexus_name(cur->nex), cur->joined);
nref += 1;
}
fprintf(xnf, " )\n"); /* end the (contents ) sexp */
fprintf(xnf, " )\n"); /* end the (view ) sexp */
fprintf(xnf, " )\n"); /* end the (cell ) sexp */
fprintf(xnf, " )\n"); /* end the (library ) sexp */
/* Make an instance of the defined object */
fprintf(xnf, " (design %s\n", ivl_scope_name(root));
fprintf(xnf, " (cellRef %s (libraryRef DESIGN))\n",
ivl_scope_name(root));
if (part)
fprintf(xnf, " (property PART (string \"%s\"))\n", part);
fprintf(xnf, " )\n");
fprintf(xnf, ")\n"); /* end the (edif ) sexp */
}
/*
* This is the main entry point that ivl uses to invoke me, the code
* generator.
*/
int target_design(ivl_design_t des)
{
ivl_scope_t root = ivl_design_root(des);
const char*path = ivl_design_flag(des, "-o");
xnf = fopen(path, "w");
if (xnf == 0) {
perror(path);
return -1;
}
part = ivl_design_flag(des, "part");
if (part && (part[0] == 0))
part = 0;
arch = ivl_design_flag(des, "arch");
if (arch && (arch[0] == 0))
arch = 0;
if (arch == 0)
arch = "lpm";
device = device_from_arch(arch);
if (device == 0) {
fprintf(stderr, "Unknown architecture arch=%s\n", arch);
return -1;
}
/* Call the device driver to generate the netlist header. */
device->show_header(des);
/* Catch any behavioral code that is left, and write warnings
that it is not supported. */
ivl_design_process(des, show_process, 0);
/* Get the pads from the design, and draw them to connect to
the associated signals. */
show_pads(root);
/* Scan the scopes, looking for gates to draw into the output
netlist. */
show_scope_gates(root, 0);
show_constants(des);
/* Call the device driver to close out the file. */
device->show_footer(des);
fclose(xnf);
xnf = 0;
return 0;
}
static void generic_show_header(ivl_design_t des)
{
ivl_scope_t root = ivl_design_root(des);
fprintf(xnf, "LCANET,6\n");
fprintf(xnf, "PROG,iverilog,$Name: $,\"Icarus Verilog/fpga.tgt\"\n");
if (part && (part[0]!=0)) {
fprintf(xnf, "PART,%s\n", part);
}
show_root_ports_xnf(root);
}
/* Ivl entry point. */
int target_design(ivl_design_t des)
{
design = des;
output = fopen(ivl_design_flag(design, "-o"), "w");
if (output == 0) {
/*
perror("** ERROR: Can not opening output file \"%s\".\n\n", ivl_design_flag(design, "-o"));
*/
perror(ivl_design_flag(design, "-o"));
return -1;
}
level = 0;
build_hierarchy(ivl_design_root(design), 0);
design = 0;
fclose(output);
output = 0;
return 0;
}
static void edif_show_header_generic(ivl_design_t des, const char*library)
{
ivl_scope_t root = ivl_design_root(des);
/* write the primitive header */
fprintf(xnf, "(edif %s\n", ivl_scope_name(root));
fprintf(xnf, " (edifVersion 2 0 0)\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (keywordMap (keywordLevel 0))\n");
fprintf(xnf, " (status\n");
fprintf(xnf, " (written\n");
fprintf(xnf, " (timeStamp 0 0 0 0 0 0)\n");
fprintf(xnf, " (author \"unknown\")\n");
fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
/* Write out the external references here? */
fputs(library, xnf);
/* Write out the library header */
fprintf(xnf, " (library DESIGN\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (technology (numberDefinition))\n");
/* The root module is a cell in the library. */
fprintf(xnf, " (cell %s\n", ivl_scope_name(root));
fprintf(xnf, " (cellType GENERIC)\n");
fprintf(xnf, " (view net\n");
fprintf(xnf, " (viewType NETLIST)\n");
fprintf(xnf, " (interface\n");
show_root_ports_edif(root);
fprintf(xnf, " )\n"); /* end the (interface ) sexp */
fprintf(xnf, " (contents\n");
}
/*
* This is the main entry point that Icarus Verilog calls to generate
* code for a pal.
*/
int target_design(ivl_design_t des)
{
unsigned idx;
const char*part;
ivl_scope_t root;
/* Get the part type from the design, using the "part"
key. Given the part type, try to open the pal description
so that we can figure out the device. */
part = ivl_design_flag(des, "part");
if ((part == 0) || (*part == 0)) {
fprintf(stderr, "error: part must be specified. Specify a\n");
fprintf(stderr, " : type with the -fpart=<type> option.\n");
return -1;
}
pal = pal_alloc(part);
if (pal == 0) {
fprintf(stderr, "error: %s is not a valid part type.\n", part);
return -1;
}
assert(pal);
pins = pal_pins(pal);
assert(pins > 0);
/* Allocate the pin array, ready to start assigning resources. */
bind_pin = calloc(pins, sizeof (struct pal_bind_s));
/* Connect all the macrocells that drive pins to the pin that
they drive. This doesn't yet look at the design, but is
initializing the bind_pin array with part information. */
for (idx = 0 ; idx < pal_sops(pal) ; idx += 1) {
pal_sop_t sop = pal_sop(pal, idx);
int spin = pal_sop_pin(sop);
if (spin == 0)
continue;
assert(spin > 0);
bind_pin[spin-1].sop = sop;
}
/* Get pin assignments from the user. This is the first and
most constrained step. Everything else must work around the
results of these bindings. */
root = ivl_design_root(des);
get_pad_bindings(root, 0);
if (pal_errors) {
fprintf(stderr, "PAD assignment failed.\n");
pal_free(pal);
return -1;
}
/* Run through the assigned output pins and absorb the output
enables that are connected to them. */
absorb_pad_enables();
/* Scan all the registers, and assign them to
macro-cells. */
root = ivl_design_root(des);
fit_registers(root, 0);
if (pal_errors) {
fprintf(stderr, "Register fitting failed.\n");
pal_free(pal);
return -1;
}
fit_logic();
if (pal_errors) {
fprintf(stderr, "Logic fitting failed.\n");
pal_free(pal);
return -1;
}
dump_final_design(stdout);
emit_jedec(ivl_design_flag(des, "-o"));
pal_free(pal);
return 0;
}
static void lpm_show_header(ivl_design_t des)
{
unsigned idx;
ivl_scope_t root = ivl_design_root(des);
unsigned sig_cnt = ivl_scope_sigs(root);
unsigned nports = 0, pidx;
/* Count the ports I'm going to use. */
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
nports += ivl_signal_pins(sig);
}
/* Create the base edf object. */
edf = edif_create(ivl_scope_basename(root), nports);
pidx = 0;
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
edif_joint_t jnt;
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
if (ivl_signal_pins(sig) == 1) {
edif_portconfig(edf, pidx, ivl_signal_basename(sig),
ivl_signal_port(sig));
assert(ivl_signal_pins(sig) == 1);
jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
edif_port_to_joint(jnt, edf, pidx);
} else {
const char*name = ivl_signal_basename(sig);
ivl_signal_port_t dir = ivl_signal_port(sig);
char buf[128];
unsigned bit;
for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
const char*tmp;
sprintf(buf, "%s[%u]", name, bit);
tmp = strdup(buf);
edif_portconfig(edf, pidx+bit, tmp, dir);
jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
edif_port_to_joint(jnt, edf, pidx+bit);
}
}
pidx += ivl_signal_pins(sig);
}
assert(pidx == nports);
xlib = edif_xlibrary_create(edf, "LPM_LIBRARY");
}
