int sec_init(void)
{
int ret = 0;
#ifdef CONFIG_PHYS_64BIT
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
uint32_t mcr = sec_in32(&sec->mcfgr);
sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT);
#endif
ret = jr_init();
if (ret < 0) {
printf("SEC initialization failed\n");
return -1;
}
if (get_rng_vid() >= 4) {
if (rng_init() < 0) {
printf("RNG instantiation failed\n");
return -1;
}
printf("SEC: RNG instantiated\n");
}
return ret;
}
int sec_init(void)
{
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
#ifdef CONFIG_FSL_CORENET
uint32_t liodnr;
uint32_t liodn_ns;
uint32_t liodn_s;
#endif
/*
* Modifying CAAM Read/Write Attributes
* For LS2080A
* For AXI Write - Cacheable, Write Back, Write allocate
* For AXI Read - Cacheable, Read allocate
* Only For LS2080a, to solve CAAM coherency issues
*/
#ifdef CONFIG_LS2080A
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
#else
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#endif
#ifdef CONFIG_PHYS_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
#ifdef CONFIG_FSL_CORENET
liodnr = sec_in32(&sec->jrliodnr[0].ls);
liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
#endif
ret = jr_init();
if (ret < 0) {
printf("SEC initialization failed\n");
return -1;
}
#ifdef CONFIG_FSL_CORENET
ret = sec_config_pamu_table(liodn_ns, liodn_s);
if (ret < 0)
return -1;
pamu_enable();
#endif
if (get_rng_vid() >= 4) {
if (rng_init() < 0) {
printf("RNG instantiation failed\n");
return -1;
}
printf("SEC: RNG instantiated\n");
}
return ret;
}
