int board_phy_config(struct phy_device *phydev)
{
int ret;
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
if (ret)
return ret;
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
static int ksz9021_config_init(struct phy_device *phydev)
{
u16 val;
/* clock and control data pad skew - register = 0x104 */
val = (0x0 << MII_KSZ9021_EXT_RGMII_RXC_SHIFT)
| (0x0 << MII_KSZ9021_EXT_RGMII_RX_DV_SHIFT)
| (0x7 << MII_KSZ9021_EXT_RGMII_TXC_SHIFT)
| (0x7 << MII_KSZ9021_EXT_RGMII_TX_EN_SHIFT);
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, val);
/* rx data pad skew - register = 0x105 */
val = (0x0 << MII_KSZ90x1_EXT_RGMII_RX3_SHIFT)
| (0x0 << MII_KSZ90x1_EXT_RGMII_RX2_SHIFT)
| (0x0 << MII_KSZ90x1_EXT_RGMII_RX1_SHIFT)
| (0x0 << MII_KSZ90x1_EXT_RGMII_RX0_SHIFT);
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, val);
/* tx data pad skew - register = 0x106 */
val = (0x7 << MII_KSZ90x1_EXT_RGMII_TX3_SHIFT)
| (0x7 << MII_KSZ90x1_EXT_RGMII_TX2_SHIFT)
| (0x7 << MII_KSZ90x1_EXT_RGMII_TX1_SHIFT)
| (0x7 << MII_KSZ90x1_EXT_RGMII_TX0_SHIFT);
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/* min rx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/* board specific timings for GMAC */
if (has_gmac()) {
/* rx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x2222);
/* tx data delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x2222);
/* rx/tx clock delay */
ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf2f4);
}
/* always run the PHY's config routine */
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
int fec_init(unsigned phy_mask, struct enet* enet)
{
struct eth_device *edev;
struct phy_device *phydev;
struct mii_dev *bus;
int ret = 0;
struct eth_device _eth;
/* create and fill edev struct */
edev = &_eth;
memset(edev, 0, sizeof(*edev));
edev->priv = (void*)enet;
edev->write_hwaddr = NULL;
/* Alocate the mdio bus */
bus = mdio_alloc();
if (!bus) {
return -1;
}
bus->read = fec_phy_read;
bus->write = fec_phy_write;
bus->priv = enet;
strcpy(bus->name, edev->name);
ret = mdio_register(bus);
if (ret) {
free(bus);
return -1;
}
/****** Configure phy ******/
phydev = phy_connect_by_mask(bus, phy_mask, edev, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
return -1;
}
/* min rx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
/* min tx data delay */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
/* max rx/tx clock delay, min rx/tx control */
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
ksz9021_config(phydev);
/* Start up the PHY */
ret = ksz9021_startup(phydev);
if (ret) {
printf("Could not initialize PHY %s\n", phydev->dev->name);
return ret;
}
printf("\n * Link speed: %4i Mbps, ", phydev->speed);
if(phydev->duplex == DUPLEX_FULL){
enet_set_speed(enet, phydev->speed, 1);
printf("full-duplex *\n");
}else{
enet_set_speed(enet, phydev->speed, 0);
printf("half-duplex *\n");
}
udelay(100000);
return 0;
}
static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
int devaddr, int regnum, u16 val)
{
return ksz9021_phy_extended_write(phydev, regnum, val);
}
