int cleanup_before_linux(void)
{
unsigned int i;
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts();
/* turn off I/D-cache */
icache_disable();
dcache_disable();
/* invalidate I-cache */
cache_flush();
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
#ifndef CONFIG_L2_OFF
l2_cache_enable();
#endif
return 0;
}
int cleanup_before_linux(void)
{
unsigned int i;
#ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE
extern void clear_mfgmode_mem(void);
clear_mfgmode_mem();
#endif
#ifdef CONFIG_VIDEO_MX5
ipu_disable_channel(MEM_BG_SYNC);
ipu_uninit_channel(MEM_BG_SYNC);
#endif
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts();
/* flush cache */
cache_flush();
/* turn off I/D-cache */
icache_disable();
/* invalidate D-cache */
dcache_disable();
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2_cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
/* turn off MMU */
MMU_OFF();
#ifndef CONFIG_L2_OFF
l2_cache_enable();
#endif
return 0;
}
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with SRAM stack.
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
/*
* Right now flushing at low MPU speed.
* Need to move after clock init
*/
invalidate_dcache(get_device_type());
#ifdef CONFIG_L2_OFF
l2_cache_disable();
#else
l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
* Currently SMI in Kernel on ES2 devices seems to have an issue
* Once that is resolved, we can postpone this config to kernel
*/
if (get_device_type() == GP_DEVICE)
setup_auxcr();
set_muxconf_regs();
sdelay(100);
prcm_init();
per_clocks_enable();
#ifdef CONFIG_USB_EHCI_OMAP
ehci_clocks_enable();
#endif
#ifdef CONFIG_SPL_BUILD
preloader_console_init();
timer_init();
#endif
if (!in_sdram)
mem_init();
}
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with SRAM stack.
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
/*
* Right now flushing at low MPU speed.
* Need to move after clock init
*/
v7_flush_dcache_all(get_device_type());
#ifndef CONFIG_ICACHE_OFF
icache_enable();
#endif
#ifdef CONFIG_L2_OFF
l2_cache_disable();
#else
l2_cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
* Currently SMI in Kernel on ES2 devices seems to have an issue
* Once that is resolved, we can postpone this config to kernel
*/
if (get_device_type() == GP_DEVICE)
setup_auxcr();
set_muxconf_regs();
delay(100);
prcm_init();
per_clocks_enable();
if (!in_sdram)
sdrc_init();
}
/*
* early system init of muxing and clocks.
*/
void s_init(u32 in_ddr)
{
/* Can be removed as A8 comes up with L2 enabled */
l2_cache_enable();
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
__raw_writel(0xAAAA, WDT_WSPR);
while(__raw_readl(WDT_WWPS) != 0x0);
__raw_writel(0x5555, WDT_WSPR);
while(__raw_readl(WDT_WWPS) != 0x0);
/* Setup the PLLs and the clocks for the peripherals */
#ifdef CONFIG_SETUP_PLL
pll_init();
#endif
#ifdef CONFIG_AM335X_CONFIG_DDR
if (!in_ddr)
config_am335x_ddr();
#endif
}
