/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with SRAM stack.
**********************************************************/
void s_init(void)
{
int i;
int external_boot = 0;
int in_sdram = running_in_sdram();
watchdog_init();
external_boot = (get_boot_type() == 0x1F) ? 1 : 0;
/* Right now flushing at low MPU speed. Need to move after clock init */
v7_flush_dcache_all(get_device_type(), external_boot);
try_unlock_memory();
if (cpu_is_3410()) {
/* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */
__asm__ __volatile__("mov %0, #0xFC":"=r" (i));
__asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i));
}
#ifndef CONFIG_ICACHE_OFF
icache_enable();
#endif
#ifdef CONFIG_L2_OFF
l2cache_disable();
#else
l2cache_enable();
#endif
set_muxconf_regs();
delay(100);
/* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
/* Currently SMI in Kernel on ES2 devices seems to have an isse
* Once that is resolved, we can postpone this config to kernel
*/
setup_auxcr(get_device_type(), external_boot);
prcm_init();
per_clocks_enable();
}
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called path is with SRAM stack.
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
/*
* Right now flushing at low MPU speed.
* Need to move after clock init
*/
v7_flush_dcache_all(get_device_type());
#ifndef CONFIG_ICACHE_OFF
icache_enable();
#endif
#ifdef CONFIG_L2_OFF
l2cache_disable();
#else
l2cache_enable();
#endif
/*
* Writing to AuxCR in U-boot using SMI for GP DEV
* Currently SMI in Kernel on ES2 devices seems to have an issue
* Once that is resolved, we can postpone this config to kernel
*/
if (get_device_type() == GP_DEVICE)
setup_auxcr();
set_muxconf_regs();
delay(100);
prcm_init();
per_clocks_enable();
if (!in_sdram)
sdrc_init();
}
/*************************************************************************
* int do_l2cache()
*
************************************************************************/
int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
{
switch (argc) {
case 2: /* on / off */
switch (on_off(argv[1])) {
case 0: l2cache_disable();
break;
case 1: l2cache_enable();
break;
}
/* FALL TROUGH */
case 1: /* get status */
printf ("L2 Cache is %s\n",
l2cache_status() ? "ON" : "OFF");
return 0;
default:
cmd_usage(cmdtp);
return 1;
}
return 0;
}
int cleanup_before_linux(void)
{
unsigned int i;
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts();
/* turn off I/D-cache */
icache_disable();
dcache_disable();
/* invalidate I-cache */
cache_flush();
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2cache_disable();
/* invalidate L2 cache also */
// v7_flush_dcache_all(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
#ifndef CONFIG_L2_OFF
l2cache_enable();
#endif
#ifdef CFG_MMU_HANDLEOK
mmu_turnoff();
#endif
return 0;
}
