Ejemplo n.º 1
0
static void __init realview_pbx_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	if (core_tile_pbxa9mp()) {
		void __iomem *l2x0_base =
			__io_address(REALVIEW_PBX_TILE_L220_BASE);

		
		writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
		writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);

		
		l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
	}
#endif

	realview_flash_register(realview_pbx_flash_resources,
				ARRAY_SIZE(realview_pbx_flash_resources));
	realview_eth_register(NULL, realview_pbx_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	platform_device_register(&realview_cf_device);
	realview_usb_register(realview_pbx_isp1761_resources);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
}
static void __init realview_eb_init(void)
{
	int i;

	if (core_tile_eb11mp() || core_tile_a9mp()) {
		realview_eb11mp_fixup();

#ifdef CONFIG_CACHE_L2X0
		/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
		 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
		l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
#endif
		platform_device_register(&pmu_device);
	}

	realview_flash_register(&realview_eb_flash_resource, 1);
	platform_device_register(&realview_i2c_device);
	platform_device_register(&char_lcd_device);
	eth_device_register();
	realview_usb_register(realview_eb_isp1761_resources);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
}
static int __init exynos4_l2x0_cache_init(void)
{
	u32 tag_latency = 0x110;
	u32 data_latency = soc_is_exynos4210() ? 0x110 : 0x120;
	u32 prefetch = (soc_is_exynos4412() &&
			samsung_rev() >= EXYNOS4412_REV_1_0) ?
			0x71000007 : 0x30000007;
	u32 aux_val = 0x7C470001;
	u32 aux_mask = 0xC200FFFF;

#ifdef CONFIG_ARM_TRUSTZONE
	exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);
	exynos_smc(SMC_CMD_L2X0SETUP2,
		   L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
		   aux_val, aux_mask);
	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
	exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
	__raw_writel(tag_latency, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
	__raw_writel(data_latency, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
	__raw_writel(prefetch, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
	__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
		     S5P_VA_L2CC + L2X0_POWER_CTRL);
#endif

	l2x0_init(S5P_VA_L2CC, aux_val, aux_mask);

#ifdef CONFIG_ARM_TRUSTZONE
#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
	outer_cache.set_debug = exynos4_l2x0_set_debug;
#endif
#endif

	return 0;
}
Ejemplo n.º 4
0
void __init r8a7779_add_standard_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 64K*16way */
	l2x0_init((void __iomem __force *)(0xf0100000), 0x40470000, 0x82000fff);
#endif
	r8a7779_pm_init();

	r8a7779_init_pm_domain(&r8a7779_sh4a);
	r8a7779_init_pm_domain(&r8a7779_sgx);
	r8a7779_init_pm_domain(&r8a7779_vdp1);
	r8a7779_init_pm_domain(&r8a7779_impx3);

	platform_add_devices(r8a7779_early_devices,
			    ARRAY_SIZE(r8a7779_early_devices));
	platform_add_devices(r8a7779_late_devices,
			    ARRAY_SIZE(r8a7779_late_devices));

	r8a7779_add_device_to_domain(&r8a7779_sgx, &sgx_device);
	pm_clk_add(&sgx_device.dev, "sgx");

#ifdef CONFIG_RENESAS_RCAR_PCI
	rcar_pcie_init(&pcie_device);
#endif
}
Ejemplo n.º 5
0
/*!
 * Post CPU init code
 *
 * @return 0 always
 */
static int __init post_cpu_init(void)
{
	void *l2_base;
	unsigned long aips_reg;

	/* Initialize L2 cache */
	l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
	if (l2_base)
		l2x0_init(l2_base, 0x00030024, 0x00000000);

	/*
	 * S/W workaround: Clear the off platform peripheral modules
	 * Supervisor Protect bit for SDMA to access them.
	 */
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
	aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
	aips_reg &= 0x00FFFFFF;
	__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
	aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
	aips_reg &= 0x00FFFFFF;
	__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));

	return 0;
}
Ejemplo n.º 6
0
static void __init sdp1004_l2c_init(void)
{
	void __iomem *base = (void __iomem*)VA_L2C_BASE;
	u32 v;

	/* prefetch control */
	v = readl (base + L2C310_PCR);
	v |= L2C310_PCR_IPF | L2C310_PCR_DPF;
	v |= L2C310_PCR_DROP | L2C310_PCR_IDLF;
#ifndef CONFIG_SDP_ARM_PL310_ERRATA_752271
	if(sdp_get_revision_id() > 0)
		v |= L2C310_PCR_DLF;
	else
		v &= ~(L2C310_PCR_DLF);
#endif

	v &= ~0x1f;
	printk (KERN_CRIT "prefetch=0x%08x\n", v);
	writel (v, base + L2C310_PCR);

	/* tag RAM latency */
	writel (0, base + L2C310_TRLCR);

	/* data RAM letency */	
	writel (0, base + L2C310_DRLCR);

	/* Data/Inst prefetch enable, random replacement */
	l2x0_init (base, L2C310_AUX_IPF | L2C310_AUX_DPF, ~(L2C310_AUX_RR));
}
Ejemplo n.º 7
0
static void __init hawaii_l2x0_init(void)
{
	void __iomem *l2cache_base = (void __iomem *)(KONA_L2C_VA);
	u32 val;
	u32 aux_val = 0x00050000;
	u32 aux_mask = 0xfff0ffff;

	/*
	 * Enable L2 if it is not already enabled by the ROM code.
	 */
	val = readl(l2cache_base + L2X0_CTRL);
	val = val & 0x1;
	if (val == 0)
  {
      /* TURN ON THE L2 CACHE */
#ifdef CONFIG_MOBICORE_DRIVER
      secure_api_call(SMC_CMD_L2X0SETUP2, 0, aux_val, aux_mask, 0);
      secure_api_call(SMC_CMD_L2X0INVALL, 0, 0, 0, 0);
      secure_api_call(SMC_CMD_L2X0CTRL, 1, 0, 0, 0);
#else
      //secure_api_call_init();
      secure_api_call(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
#endif
   }
	/*
	 * 32KB way size, 16-way associativity
	 */
	l2x0_init(l2cache_base, aux_val, aux_mask);

}
static void __init sh73a0_generic_init(void)
{
#ifdef CONFIG_CACHE_L2X0
	/* Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
}
Ejemplo n.º 9
0
static void __init realview_pb1176_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	/* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
	l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
#endif

	clk_register(&realview_clcd_clk);

	realview_flash_register(realview_pb1176_flash_resources,
				PB1176_FLASH_BLOCKS);
	realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	realview_usb_register(realview_pb1176_isp1761_resources);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
}
Ejemplo n.º 10
0
static void __init realview_pbx_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	if (core_tile_pbxa9mp()) {
		void __iomem *l2x0_base =
			__io_address(REALVIEW_PBX_TILE_L220_BASE);

		/* set RAM latencies to 1 cycle for eASIC */
		writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
		writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);

		/* 16KB way size, 8-way associativity, parity disabled
		 * Bits:  .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
		l2x0_init(l2x0_base, 0x02520000, 0xc0000fff);
		platform_device_register(&pmu_device);
	}
#endif

	realview_flash_register(realview_pbx_flash_resources,
				ARRAY_SIZE(realview_pbx_flash_resources));
	realview_eth_register(NULL, realview_pbx_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	platform_device_register(&realview_cf_device);
	platform_device_register(&realview_leds_device);
	realview_usb_register(realview_pbx_isp1761_resources);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
}
Ejemplo n.º 11
0
void __init tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;

#ifndef CONFIG_TRUSTED_FOUNDATIONS
   /*
   ISSUE : Some registers of PL310 controler must be called from Secure context!
            When called form Normal we obtain an abort.
            Instructions that must be called in Secure :
               - Tag and Data RAM Latency Control Registers (0x108 & 0x10C) must be written in Secure.
        
   The following section of code has been regrouped in the implementation of "l2x0_init".
   The "l2x0_init" will in fact call an SMC intruction to switch from Normal context to Secure context.
   The configuration and activation will be done in Secure.
   */
	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
	writel(7, p + L2X0_PREFETCH_OFFSET);
#endif

	l2x0_init(p, 0x7C480001, 0x8200c3fe);
#endif

}
Ejemplo n.º 12
0
static void __init realview_pb11mp_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	/* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
	 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
	l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
#endif

	realview_flash_register(realview_pb11mp_flash_resource,
				ARRAY_SIZE(realview_pb11mp_flash_resource));
	realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	platform_device_register(&realview_cf_device);
	realview_usb_register(realview_pb11mp_isp1761_resources);
	platform_device_register(&pmu_device);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
	realview_reset = realview_pb11mp_reset;
}
Ejemplo n.º 13
0
/*!
 * Post CPU init code
 *
 * @return 0 always
 */
static int __init post_cpu_init(void)
{
	void *l2_base;
	volatile unsigned long aips_reg;

	/* Initialize L2 cache */
	l2_base = ioremap(L2CC_BASE_ADDR, SZ_4K);
	if (l2_base) {
		l2x0_init(l2_base, 0x0003001B, 0x00000000);
	}

	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x40));
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x44));
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x48));
	__raw_writel(0x0, IO_ADDRESS(AIPS1_BASE_ADDR + 0x4C));
	aips_reg = __raw_readl(IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));
	aips_reg &= 0x00FFFFFF;
	__raw_writel(aips_reg, IO_ADDRESS(AIPS1_BASE_ADDR + 0x50));

	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x40));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x44));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x48));
	__raw_writel(0x0, IO_ADDRESS(AIPS2_BASE_ADDR + 0x4C));
	aips_reg = __raw_readl(IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));
	aips_reg &= 0x00FFFFFF;
	__raw_writel(aips_reg, IO_ADDRESS(AIPS2_BASE_ADDR + 0x50));

	return 0;
}
Ejemplo n.º 14
0
int mxc_init_l2x0(void)
{
	unsigned int val;

	#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002

	val = readl(IOMUXC_GPR11);
	if (cpu_is_mx6sl() && (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM)) {
		/* L2 cache configured as OCRAM, reset it */
		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
		writel(val, IOMUXC_GPR11);
	}

	writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
	writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));

	val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
	val |= 0x40800000;
	writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
	val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL));
	val |= L2X0_DYNAMIC_CLK_GATING_EN;
	val |= L2X0_STNDBY_MODE_EN;
	writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL));

	l2x0_init(IO_ADDRESS(L2_BASE_ADDR), 0x0, ~0x00000000);
	return 0;
}
Ejemplo n.º 15
0
static int __init msm7x27x_cache_init(void)
{
	int aux_ctrl = 0;
	int pctrl = 0;

	/* Way Size 010(0x2) 32KB */
	aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | \
		   (0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
		   (0x1 << L2X0_AUX_CTRL_EVNT_MON_BUS_EN_SHIFT);

	if (cpu_is_msm8625()) {
		/* Way Size 011(0x3) 64KB */
		aux_ctrl |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | \
			    (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | \
			    (0X1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | \
			    (0x1 << L2X0_AUX_CTRL_L2_FORCE_NWA_SHIFT);

		/* Write Prefetch Control settings */
		pctrl = readl_relaxed(MSM_L2CC_BASE + L2X0_PREFETCH_CTRL);
		pctrl |= (0x3 << L2X0_PREFETCH_CTRL_OFFSET_SHIFT) | \
			 (0x1 << L2X0_PREFETCH_CTRL_WRAP8_INC_SHIFT) | \
			 (0x1 << L2X0_PREFETCH_CTRL_WRAP8_SHIFT);
		writel_relaxed(pctrl , MSM_L2CC_BASE + L2X0_PREFETCH_CTRL);
	}

	l2x0_init(MSM_L2CC_BASE, aux_ctrl, L2X0_AUX_CTRL_MASK);
	if (cpu_is_msm8625()) {
		pctrl = readl_relaxed(MSM_L2CC_BASE + L2X0_PREFETCH_CTRL);
		pr_info("Prfetch Ctrl: 0x%08x\n", pctrl);
	}

	return 0;
}
Ejemplo n.º 16
0
void tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
	u32 aux_ctrl;

#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
	writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
	writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);

#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
#ifdef CONFIG_TEGRA_SILICON_PLATFORM
	/* PL310 RAM latency is CPU dependent. NOTE: Changes here
	   must also be reflected in __cortex_a9_l2x0_restart */

	if (is_lp_cluster()) {
		writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
		writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
	} else {
		writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
		writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
	}
#else
	writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
	writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
#endif
#endif
	aux_ctrl = readl(p + L2X0_CACHE_TYPE);
	aux_ctrl = (aux_ctrl & 0x700) << (17-8);
	aux_ctrl |= 0x7C000001;
	l2x0_init(p, aux_ctrl, 0x8200c3fe);
#endif
}
Ejemplo n.º 17
0
static void __init realview_pb11mp_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	/*
	 * The PL220 needs to be manually configured as the hardware
	 * doesn't report the correct sizes.
	 * 1MB (128KB/way), 8-way associativity, event monitor and
	 * parity enabled, ignore share bit, no force write allocate
	 * Bits:  .... ...0 0111 1001 0000 .... .... ....
	 */
	l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
#endif

	realview_flash_register(realview_pb11mp_flash_resource,
				ARRAY_SIZE(realview_pb11mp_flash_resource));
	realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	platform_device_register(&realview_cf_device);
	realview_usb_register(realview_pb11mp_isp1761_resources);
	platform_device_register(&pmu_device);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}
}
Ejemplo n.º 18
0
static void __init kota2_init(void)
{
	regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
				     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
	regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
				     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
	regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	pinctrl_register_mappings(kota2_pinctrl_map,
				  ARRAY_SIZE(kota2_pinctrl_map));
	sh73a0_pinmux_init();

	/* SMSC911X */
	gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
	gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */

	/* MMCIF */
	gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */

#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
#endif
	sh73a0_add_standard_devices();
	platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
}
Ejemplo n.º 19
0
static int imx6_mmu_init(void)
{
    void __iomem *l2x0_base = IOMEM(0x00a02000);
    u32 val;

    if (!cpu_is_mx6())
        return 0;

    /* Configure the L2 PREFETCH and POWER registers */
    val = readl(l2x0_base + L310_PREFETCH_CTRL);
    val |= 0x70800000;

    /*
     * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
     * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
     * But according to ARM PL310 errata: 752271
     * ID: 752271: Double linefill feature can cause data corruption
     * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
     * Workaround: The only workaround to this erratum is to disable the
     * double linefill feature. This is the default behavior.
     */
    if (cpu_is_mx6q())
        val &= ~(1 << 30 | 1 << 23);

    writel(val, l2x0_base + L310_PREFETCH_CTRL);

    l2x0_init(l2x0_base, 0x0, ~0UL);

    return 0;
}
Ejemplo n.º 20
0
void tegra_init_cache(bool init)
{
#ifdef CONFIG_TRUSTED_FOUNDATIONS
	/* enable/re-enable of L2 handled by secureos */
	return tegra_init_cache_tz(init);
#else
	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
	u32 aux_ctrl;

#if defined(CONFIG_ARCH_TEGRA_2x_SOC)
	writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
	writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);

#elif defined(CONFIG_ARCH_TEGRA_3x_SOC)
#ifdef CONFIG_TEGRA_SILICON_PLATFORM
	/* PL310 RAM latency is CPU dependent. NOTE: Changes here
	   must also be reflected in __cortex_a9_l2x0_restart */

	if (is_lp_cluster()) {
		writel(0x221, p + L2X0_TAG_LATENCY_CTRL);
		writel(0x221, p + L2X0_DATA_LATENCY_CTRL);
	} else {
		u32 speedo;

		/* relax l2-cache latency for speedos 4,5,6 (T33's chips) */
		speedo = tegra_cpu_speedo_id();
		if (speedo == 4 || speedo == 5 || speedo == 6 ||
		    speedo == 12 || speedo == 13) {
			writel(0x442, p + L2X0_TAG_LATENCY_CTRL);
			writel(0x552, p + L2X0_DATA_LATENCY_CTRL);
		} else {
			writel(0x441, p + L2X0_TAG_LATENCY_CTRL);
			writel(0x551, p + L2X0_DATA_LATENCY_CTRL);
		}
	}
#else
	writel(0x770, p + L2X0_TAG_LATENCY_CTRL);
	writel(0x770, p + L2X0_DATA_LATENCY_CTRL);
#endif
#endif
	writel(0x3, p + L2X0_POWER_CTRL);
	aux_ctrl = readl(p + L2X0_CACHE_TYPE);
	aux_ctrl = (aux_ctrl & 0x700) << (17-8);
	aux_ctrl |= 0x7C000001;
	if (init) {
		l2x0_init(p, aux_ctrl, 0x8200c3fe);
		/* use our outer_disable() routine to avoid flush */
		outer_cache.disable = tegra_l2x0_disable;
	} else {
		u32 tmp;

		tmp = aux_ctrl;
		aux_ctrl = readl(p + L2X0_AUX_CTRL);
		aux_ctrl &= 0x8200c3fe;
		aux_ctrl |= tmp;
		writel(aux_ctrl, p + L2X0_AUX_CTRL);
	}
	l2x0_enable();
#endif
}
/*
 * board init
 */
static void __init eva_init(void)
{

	r8a7740_clock_init(MD_CK0 | MD_CK2);
	eva_clock_init();

	pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
	r8a7740_pinmux_init();

	r8a7740_meram_workaround();

	/*
	 * Touchscreen
	 * TODO: Move reset GPIO over to .dts when we can reference it
	 */
	gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */

#ifdef CONFIG_CACHE_L2X0
	/* Early BRESP enable, Shared attribute override enable, 32K*8way */
	l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
#endif

	r8a7740_add_standard_devices_dt();
	r8a7740_pm_init();
}
Ejemplo n.º 22
0
/*
 *  Maps common IO regions for tcc892x.
 */
void __init tcc_map_common_io(void)
{
	iotable_init(tcc8920_io_desc, ARRAY_SIZE(tcc8920_io_desc));

	/* Normally devicemaps_init() would flush caches and tlb after
	 * mdesc->map_io(), but we must also do it here because of the CPU
	 * revision check below.
	 */
	local_flush_tlb_all();
	flush_cache_all();

	__cpu_early_init();

#ifdef CONFIG_CACHE_L2X0
	// Way size = 16KB, Associativity = 16Way
	l2x0_init(0xFA000000, 0x70130001, ~0x022C0000);
#endif

#if defined(__TODO__)
	IO_UTIL_ReadECID();
#endif

//	tcc_reserve_sdram();

	// XXX
	tca_ckc_init();
}
Ejemplo n.º 23
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static int __init ux500_l2x0_init(void)
{
	uint32_t aux_val = 0x3e000000;

	if (cpu_is_u5500())
		l2x0_base = __io_address(U5500_L2CC_BASE);
	else if (cpu_is_u8500() || cpu_is_u9540())
		l2x0_base = __io_address(U8500_L2CC_BASE);
	else
		ux500_unknown_soc();

	/* u9540's L2 has 128KB way size */
	if (cpu_is_u9540())
		aux_val |=
		(0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); /* 128KB way size */
	else
		aux_val |=
		(0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); /* 64KB way size */

	/* 8 way associativity, force WA */
	l2x0_init(l2x0_base, aux_val, 0xc0000fff);

	/* Override invalidate function */
	outer_cache.disable = ux500_l2x0_disable;
	outer_cache.inv_all = ux500_l2x0_inv_all;

	return 0;
}
Ejemplo n.º 24
0
static void __init realview_pb1176_init(void)
{
	int i;

#ifdef CONFIG_CACHE_L2X0
	
	l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
#endif

	realview_flash_register(realview_pb1176_flash_resources,
				PB1176_FLASH_BLOCKS);
	realview_eth_register(NULL, realview_pb1176_smsc911x_resources);
	platform_device_register(&realview_i2c_device);
	realview_usb_register(realview_pb1176_isp1761_resources);

	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

#ifdef CONFIG_LEDS
	leds_event = realview_leds_event;
#endif
	realview_reset = realview_pb1176_reset;
}
Ejemplo n.º 25
0
static void __init kzm_init(void)
{
	regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
				     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
	regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));

	pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));

	sh73a0_pinmux_init();

	/* SMSC */
	gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */

	/* LCDC */
	gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
	gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */

	/* Touchscreen */
	gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */

#ifdef CONFIG_CACHE_L2X0
	/* Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif

	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
	i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices));
	i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices));

	sh73a0_add_standard_devices();
	platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));

	sh73a0_pm_init();
}
Ejemplo n.º 26
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/*
 * This function is called from the board init ("init_machine").
 */
 void __init cpu8815_platform_init(void)
{
#ifdef CONFIG_CACHE_L2X0
	/* At full speed latency must be >=2, so 0x249 in low bits */
	l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff);
#endif
	 return;
}
Ejemplo n.º 27
0
 void __init cpu8815_platform_init(void)
{
#ifdef CONFIG_CACHE_L2X0
	
	l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff);
#endif
	 return;
}
Ejemplo n.º 28
0
static void __init msm7x2x_map_io(void)
{
	msm_map_common_io();

	msm_msm7x2x_allocate_memory_regions();

	if (socinfo_init() < 0)
		BUG();

#ifdef CONFIG_CACHE_L2X0
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) > 1)
		|| ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1)
		&& (SOCINFO_VERSION_MINOR(socinfo_get_version()) >= 3)))
		l2x0_init(MSM_L2CC_BASE, 0x0006801B, 0xfe000000);
	else
		l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
#endif
}
Ejemplo n.º 29
0
static void __init rhea_l2x0_init(void)
{
	void __iomem *l2cache_base = (void __iomem *)(KONA_L2C_VA);

	/*
	 * 32KB way size, 8-way associativity
	 */
	l2x0_init(l2cache_base, 0x00040000, 0xfff0ffff);
}
Ejemplo n.º 30
0
static void __init kzm_init(void)
{
	sh73a0_add_standard_devices_dt();

#ifdef CONFIG_CACHE_L2X0
	/* Shared attribute override enable, 64K*8way */
	l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
#endif
}