void
lapic_setup(int boot)
{
struct lapic *la;
u_int32_t maxlvt;
register_t saveintr;
char buf[MAXCOMLEN + 1];
la = &lapics[lapic_id()];
KASSERT(la->la_present, ("missing APIC structure"));
saveintr = intr_disable();
maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
/* Initialize the TPR to allow all interrupts. */
lapic_set_tpr(0);
/* Setup spurious vector and enable the local APIC. */
lapic_enable();
/* Program LINT[01] LVT entries. */
lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
/* Program the PMC LVT entry if present. */
if (maxlvt >= LVT_PMC)
lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
/* Program timer LVT and setup handler. */
la->lvt_timer_cache = lapic->lvt_timer =
lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
if (boot) {
snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid));
intrcnt_add(buf, &la->la_timer_count);
}
/* Setup the timer if configured. */
if (la->la_timer_mode != 0) {
KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor",
lapic_id()));
lapic_timer_set_divisor(lapic_timer_divisor);
if (la->la_timer_mode == 1)
lapic_timer_periodic(la, la->la_timer_period, 1);
else
lapic_timer_oneshot(la, la->la_timer_period, 1);
}
/* Program error LVT and clear any existing errors. */
lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error);
lapic->esr = 0;
/* XXX: Thermal LVT */
/* Program the CMCI LVT entry if present. */
if (maxlvt >= LVT_CMCI)
lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
intr_restore(saveintr);
}
static int
lapic_et_start(struct eventtimer *et,
struct bintime *first, struct bintime *period)
{
struct lapic *la;
u_long value;
la = &lapics[PCPU_GET(apic_id)];
if (et->et_frequency == 0) {
/* Start off with a divisor of 2 (power on reset default). */
lapic_timer_divisor = 2;
/* Try to calibrate the local APIC timer. */
do {
lapic_timer_set_divisor(lapic_timer_divisor);
lapic_timer_oneshot(la, APIC_TIMER_MAX_COUNT, 0);
DELAY(1000000);
value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
if (value != APIC_TIMER_MAX_COUNT)
break;
lapic_timer_divisor <<= 1;
} while (lapic_timer_divisor <= 128);
if (lapic_timer_divisor > 128)
panic("lapic: Divisor too big");
if (bootverbose)
printf("lapic: Divisor %lu, Frequency %lu Hz\n",
lapic_timer_divisor, value);
et->et_frequency = value;
et->et_min_period.sec = 0;
et->et_min_period.frac =
((0x00000002LLU << 32) / et->et_frequency) << 32;
et->et_max_period.sec = 0xfffffffeLLU / et->et_frequency;
et->et_max_period.frac =
((0xfffffffeLLU << 32) / et->et_frequency) << 32;
}
if (la->la_timer_mode == 0)
lapic_timer_set_divisor(lapic_timer_divisor);
if (period != NULL) {
la->la_timer_mode = 1;
la->la_timer_period =
(et->et_frequency * (period->frac >> 32)) >> 32;
if (period->sec != 0)
la->la_timer_period += et->et_frequency * period->sec;
lapic_timer_periodic(la, la->la_timer_period, 1);
} else {
static void
lapic_timer_calibrate(void)
{
sysclock_t value;
/* Try to calibrate the local APIC timer. */
for (lapic_timer_divisor_idx = 0;
lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
lapic_timer_divisor_idx++) {
lapic_timer_set_divisor(lapic_timer_divisor_idx);
lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
DELAY(2000000);
value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
if (value != APIC_TIMER_MAX_COUNT)
break;
}
if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
panic("lapic: no proper timer divisor?!");
lapic_cputimer_intr.freq = value / 2;
kprintf("lapic: divisor index %d, frequency %u Hz\n",
lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
}
/*
* Enable LAPIC, configure interrupts.
*/
void
lapic_init(boolean_t bsp)
{
uint32_t timer;
u_int temp;
/*
* Install vectors
*
* Since IDT is shared between BSP and APs, these vectors
* only need to be installed once; we do it on BSP.
*/
if (bsp) {
if (cpu_vendor_id == CPU_VENDOR_AMD &&
CPUID_TO_FAMILY(cpu_id) >= 0xf) {
uint32_t tcr;
/*
* Set the LINTEN bit in the HyperTransport
* Transaction Control Register.
*
* This will cause EXTINT and NMI interrupts
* routed over the hypertransport bus to be
* fed into the LAPIC LINT0/LINT1. If the bit
* isn't set, the interrupts will go to the
* general cpu INTR/NMI pins. On a dual-core
* cpu the interrupt winds up going to BOTH cpus.
* The first cpu that does the interrupt ack
* cycle will get the correct interrupt. The
* second cpu that does it will get a spurious
* interrupt vector (typically IRQ 7).
*/
outl(0x0cf8,
(1 << 31) | /* enable */
(0 << 16) | /* bus */
(0x18 << 11) | /* dev (cpu + 0x18) */
(0 << 8) | /* func */
0x68 /* reg */
);
tcr = inl(0xcfc);
if ((tcr & 0x00010000) == 0) {
kprintf("LAPIC: AMD LINTEN on\n");
outl(0xcfc, tcr|0x00010000);
}
outl(0x0cf8, 0);
}
/* Install a 'Spurious INTerrupt' vector */
setidt_global(XSPURIOUSINT_OFFSET, Xspuriousint,
SDT_SYSIGT, SEL_KPL, 0);
/* Install a timer vector */
setidt_global(XTIMER_OFFSET, Xtimer,
SDT_SYSIGT, SEL_KPL, 0);
/* Install an inter-CPU IPI for TLB invalidation */
setidt_global(XINVLTLB_OFFSET, Xinvltlb,
SDT_SYSIGT, SEL_KPL, 0);
/* Install an inter-CPU IPI for IPIQ messaging */
setidt_global(XIPIQ_OFFSET, Xipiq,
SDT_SYSIGT, SEL_KPL, 0);
/* Install an inter-CPU IPI for CPU stop/restart */
setidt_global(XCPUSTOP_OFFSET, Xcpustop,
SDT_SYSIGT, SEL_KPL, 0);
}
/*
* Setup LINT0 as ExtINT on the BSP. This is theoretically an
* aggregate interrupt input from the 8259. The INTA cycle
* will be routed to the external controller (the 8259) which
* is expected to supply the vector.
*
* Must be setup edge triggered, active high.
*
* Disable LINT0 on BSP, if I/O APIC is enabled.
*
* Disable LINT0 on the APs. It doesn't matter what delivery
* mode we use because we leave it masked.
*/
temp = lapic->lvt_lint0;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
if (bsp) {
temp |= APIC_LVT_DM_EXTINT;
if (ioapic_enable)
temp |= APIC_LVT_MASKED;
} else {
temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
}
lapic->lvt_lint0 = temp;
/*
* Setup LINT1 as NMI.
*
* Must be setup edge trigger, active high.
*
* Enable LINT1 on BSP, if I/O APIC is enabled.
*
* Disable LINT1 on the APs.
*/
temp = lapic->lvt_lint1;
temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
if (bsp && ioapic_enable)
temp &= ~APIC_LVT_MASKED;
lapic->lvt_lint1 = temp;
/*
* Mask the LAPIC error interrupt, LAPIC performance counter
* interrupt.
*/
lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
/*
* Set LAPIC timer vector and mask the LAPIC timer interrupt.
*/
timer = lapic->lvt_timer;
timer &= ~APIC_LVTT_VECTOR;
timer |= XTIMER_OFFSET;
timer |= APIC_LVTT_MASKED;
lapic->lvt_timer = timer;
/*
* Set the Task Priority Register as needed. At the moment allow
* interrupts on all cpus (the APs will remain CLId until they are
* ready to deal).
*/
temp = lapic->tpr;
temp &= ~APIC_TPR_PRIO; /* clear priority field */
lapic->tpr = temp;
/*
* Enable the LAPIC
*/
temp = lapic->svr;
temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
/*
* Set the spurious interrupt vector. The low 4 bits of the vector
* must be 1111.
*/
if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
temp &= ~APIC_SVR_VECTOR;
temp |= XSPURIOUSINT_OFFSET;
lapic->svr = temp;
/*
* Pump out a few EOIs to clean out interrupts that got through
* before we were able to set the TPR.
*/
lapic->eoi = 0;
lapic->eoi = 0;
lapic->eoi = 0;
if (bsp) {
lapic_timer_calibrate();
if (lapic_timer_enable) {
cputimer_intr_register(&lapic_cputimer_intr);
cputimer_intr_select(&lapic_cputimer_intr, 0);
}
} else {
lapic_timer_set_divisor(lapic_timer_divisor_idx);
}
if (bootverbose)
apic_dump("apic_initialize()");
}