/*****************************************************************************
 * FUNCTION
 *    mau_config
 * DESCRIPTION
 *    1. Call mau_start_monitor to set MAU related register.
 * PARAMETERS
 *	param1 : [IN] MTK_MAU_CONFIG* pMauConf
 *				MAU setting configuration.
 * RETURNS
 *    Type: Integer.  zero mean success and others mean fail.
 ****************************************************************************/
int mau_config(MTK_MAU_CONFIG* pMauConf)
{

    SMIMSG("mau config: larb=%d,entry=%d,rd=%d,wr=%d,vir=%d,start=0x%x,end=0x%x,port_msk=0x%x\n",
        pMauConf->larb, pMauConf->entry, pMauConf->monitor_read, pMauConf->monitor_write,
        pMauConf->virt,pMauConf->start, pMauConf->end, pMauConf->port_msk);

    if(pMauConf->larb > SMI_LARB_NR ||
        pMauConf->entry > MAU_ENTRY_NR)
    {
        SMIERR("config:larb=%d,entry=%d\n", pMauConf->larb, pMauConf->entry);
        return -1;
    }


    larb_clock_on(pMauConf->larb, "MAU");
    mau_start_monitor(pMauConf->larb,
                      pMauConf->entry,
                      !!(pMauConf->monitor_read),
                      !!(pMauConf->monitor_write),
                      !!(pMauConf->virt),
                      pMauConf->start,
                      pMauConf->end,
                      pMauConf->port_msk); 
    
    larb_clock_off(pMauConf->larb, "MAU");
    return 0;
}
Ejemplo n.º 2
0
int smi_common_init(void)
{
    int i;
/*
    for( i=0 ; i < SMI_LARB_NR ; i++)
    {
        pLarbRegBackUp[i] = (unsigned int*)kmalloc(LARB_BACKUP_REG_SIZE, GFP_KERNEL|__GFP_ZERO);
        if(pLarbRegBackUp[i]==NULL)
        {
        	  SMIERR("pLarbRegBackUp kmalloc fail %d \n", i);
        }  
    }
*/
    /** make sure all larb power is on before we register callback func.
        then, when larb power is first off, default register value will be backed up.
    **/     

    for( i=0 ; i < SMI_LARB_NR ; i++)
    {
        larb_clock_on(i);
    }

    register_larb_monitor(&larb_monitor_handler);
    
    for( i=0 ; i < SMI_LARB_NR ; i++)
    {
        larb_clock_off(i);
    }
    
    return 0;
}
/*****************************************************************************
 * FUNCTION
 *    mau_dump_status
 * DESCRIPTION
 *    1. Dump register in MAU related register.
 *    2. Show MAU status 
 * PARAMETERS
 *	param1 : [IN] MTK_MAU_CONFIG* pMauConf
 *				MAU setting configuration.
 * RETURNS
 *    None.
 ****************************************************************************/
void mau_dump_status(const int larb)
{
    unsigned int larb_base;
    unsigned int regval;
    int i;
    
    larb_clock_on(larb, "MAU");
        
    larb_base = gLarbBaseAddr[larb];

    //dump interrupt debug infomation
    for(i=0; i<MAU_ENTRY_NR; i++)
    {
        regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_GID(i));
        if(regval!=0)
        {
            SMIMSG("larb(%d), entry(%d)=========>\n", larb, i);
            SMIMSG("port mask = 0x%x\n", regval);
            regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
            SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n", 
                F_MAU_START_ADDR_VAL(regval), 
                F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
            regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
            SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval), 
                F_MAU_END_IS_VIR(regval));
        }
        else
        {
            SMIMSG("larb(%d), entry(%d) is free\n", larb, i);
        }


        //dump interrupt debug infomation
        regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
        if(F_MAU_STAT_ASSERT(regval))
        {
            //violation happens in this entry
            int port =  F_MAU_STAT_ID(regval);
            SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
            SMIMSG("violation by %s\n",smi_port_name[port]);
        }
        else
        {
            SMIMSG("no violation of entry %d\n", i);
        }
#if 0
        //clear interrupt status
        regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
        M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
#endif        
    }


    larb_clock_off(larb, "MAU");

}
/*****************************************************************************
 * FUNCTION
 *    mau_isr
 * DESCRIPTION
 *    1. Print MAU status, such as port ID.
 *    2. Clear interrupt status.
 * PARAMETERS
 *	  param1 : [IN] int irq
 *				  irq number.
 *	  param2 : [IN] void *dev_id
 *				  No use in this function.
 * RETURNS
 *    Type: irqreturn_t. IRQ_HANDLED mean success.
 ****************************************************************************/
static irqreturn_t mau_isr(int irq, void *dev_id)
{
    int larb,i;
    unsigned int larb_base;
    unsigned int regval;

    switch(irq)
    {
        case MT_SMI_LARB0_IRQ_ID:
            larb = 0;
            break;
        default :
            larb=0;
            SMIERR("unkown irq(%d)\n",irq);
            
    }

    larb_clock_on(larb, "MAU");
        
    larb_base = gLarbBaseAddr[larb];

    //dump interrupt debug infomation
    for(i=0; i<MAU_ENTRY_NR; i++)
    {
        regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
        if(F_MAU_STAT_ASSERT(regval))
        {
            //violation happens in this entry
            int port =  F_MAU_STAT_ID(regval);
            SMIMSG("[MAU] larb=%d, entry=%d, port=%d\n",larb,i,port);
            regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_START(i));
            SMIMSG("start_addr=0x%x, read_en=%d, write_en=%d\n", F_MAU_START_ADDR_VAL(regval), 
                F_MAU_START_IS_RD(regval), F_MAU_START_IS_WR(regval));
            regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_END(i));
            SMIMSG("end_addr=0x%x, virtual=%d\n", F_MAU_END_ADDR_VAL(regval), 
                F_MAU_END_IS_VIR(regval));
            smi_aee_print("violation by %s\n",smi_port_name[port]);
        }

        //clear interrupt status
        regval = M4U_ReadReg32(larb_base, SMI_MAU_ENTR_STAT(i));
        M4U_WriteReg32(larb_base, SMI_MAU_ENTR_STAT(i), regval);
    }

    larb_clock_off(larb, "MAU");
    return IRQ_HANDLED;
}
/*****************************************************************************
 * FUNCTION
 *    mau_init
 * DESCRIPTION
 *    1. Setup IRQ
 *    2. Call mau_enable_interrupt to enable MAU interrupt.
 * PARAMETERS
 *    None.
 * RETURNS
 *    Type: Integer.  zero mean success and others mean fail.
 ****************************************************************************/
int mau_init(void)
{
    int i;

    if(request_irq(MT_SMI_LARB0_IRQ_ID , (irq_handler_t)mau_isr, IRQF_TRIGGER_LOW, "MAU0" , NULL))
    {
        SMIERR("request MAU0 IRQ line failed");
        return -ENODEV;
    }

    for(i=0; i<SMI_LARB_NR; i++)
    {
        larb_clock_on(i, "MAU");
        mau_enable_interrupt(i);
        larb_clock_off(i, "MAU");
    }

    return 0;
}
Ejemplo n.º 6
0
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf , unsigned long * pu4LocalCnt)
{
    int i;
    unsigned long u4Concurrency = 0;
    MTK_SMI_BWC_SCEN eFinalScen;
    static MTK_SMI_BWC_SCEN ePreviousFinalScen = SMI_BWC_SCEN_CNT;

    if((SMI_BWC_SCEN_CNT <= p_conf->scenario) || (0 > p_conf->scenario))
    {
        SMIERR("Incorrect SMI BWC config : 0x%x, how could this be...\n" , p_conf->scenario);
        return -1;
    }
//Debug - S
//SMIMSG("SMI setTo%d,%s,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , ePreviousFinalScen);
//Debug - E

    spin_lock(&g_SMIInfo.SMI_lock);

    if(p_conf->b_on_off)
    {
        //turn on certain scenario
        g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] += 1;

        if(NULL != pu4LocalCnt)
        {
            pu4LocalCnt[p_conf->scenario] += 1;
        }
    }
    else
    {
        //turn off certain scenario
        if(0 == g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario])
        {
            SMIMSG("Too many turning off for global SMI profile:%d,%d\n" , p_conf->scenario , g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario]);
        }
        else
        {
            g_SMIInfo.pu4ConcurrencyTable[p_conf->scenario] -= 1;
        }

        if(NULL != pu4LocalCnt)
        {
            if(0 == pu4LocalCnt[p_conf->scenario])
            {
                SMIMSG("Process : %s did too many turning off for local SMI profile:%d,%d\n" , current->comm ,p_conf->scenario , pu4LocalCnt[p_conf->scenario]);
            }
            else
            {
                pu4LocalCnt[p_conf->scenario] -= 1;
            }
        }
    }

    for(i=0 ; i < SMI_BWC_SCEN_CNT ; i++)
    {
        if(g_SMIInfo.pu4ConcurrencyTable[i])
        {
            u4Concurrency |= (1 << i);
        }
    }

    if((1 << SMI_BWC_SCEN_VR) & u4Concurrency)
    {
        eFinalScen = SMI_BWC_SCEN_VR;
    }
    else if((1 << SMI_BWC_SCEN_VP) & u4Concurrency)
    {
        eFinalScen = SMI_BWC_SCEN_VP;
    }
    else
    {
        eFinalScen = SMI_BWC_SCEN_NORMAL;
    }

    if(ePreviousFinalScen == eFinalScen)
    {
        SMIMSG("Scen equal%d,don't change\n" , eFinalScen);
        spin_unlock(&g_SMIInfo.SMI_lock);
        return 0;
    }
    else
    {
        ePreviousFinalScen = eFinalScen;
    }

    /*turn on larb clock*/
    for( i=0 ; i < SMI_LARB_NR ; i++){
        larb_clock_on(i);
    }

    /*Bandwidth Limiter*/
    switch( eFinalScen )
    {
    case SMI_BWC_SCEN_VP:
        SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VP");
#if 1
        M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
        M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
        M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs

        M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
        M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
        M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0x961);//353/4096 maximum grant counts, soft limiter
        M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x885A25);//549/4096 maximum grant counts, hard limiter, 2 read 2 write outstanding limit

        M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
        M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
        M4U_WriteReg32(LARB0_BASE , 0x208 , 0x3);//WDMA
        M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
        M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
        M4U_WriteReg32(LARB0_BASE , 0x214 , 0x1);//MDP_WDMA
        M4U_WriteReg32(LARB0_BASE , 0x218 , 0x4);//MDP_ROTO
        M4U_WriteReg32(LARB0_BASE , 0x21C , 0x2);//MDP_ROTCO
        M4U_WriteReg32(LARB0_BASE , 0x220 , 0x2);//MDP_ROTVO

        M4U_WriteReg32(LARB1_BASE , 0x200 , 0x6);//MC
        M4U_WriteReg32(LARB1_BASE , 0x204 , 0x2);//PP
        M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
        M4U_WriteReg32(LARB1_BASE , 0x20C , 0x3);//RD
        M4U_WriteReg32(LARB1_BASE , 0x210 , 0x3);//WR
        M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
        M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP

        M4U_WriteReg32(LARB2_BASE , 0x200 , 0x1);//IMGO
        M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
        M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
        M4U_WriteReg32(LARB2_BASE , 0x20C , 0x1);//IMGI
        M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
        M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
        M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
        M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
        M4U_WriteReg32(LARB2_BASE , 0x220 , 0x2);//VENC_RD_COMV
        M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
        M4U_WriteReg32(LARB2_BASE , 0x228 , 0x4);//VENC_RCPU
        M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
        M4U_WriteReg32(LARB2_BASE , 0x230 , 0x2);//VENC_REF_LUMA
        M4U_WriteReg32(LARB2_BASE , 0x234 , 0x1);//VENC_REF_CHROMA
        M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
        M4U_WriteReg32(LARB2_BASE , 0x23C , 0x1);//VENC_CUR_LUMA
        M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA

#endif
        break;

    case SMI_BWC_SCEN_VR:
        SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_VR");
#if 1
        M4U_WriteReg32(REG_SMI_M4U_TH , 0 , ((0x2 << 15) + (0x3 << 10) + (0x4 << 5) + 0x5));// 2 non-ultra write, 3 write command , 4 non-ultra read , 5 ultra read
        M4U_WriteReg32(REG_SMI_L1LEN , 0 , 0xB);//Level 1 LARB, apply new outstanding control method, 1/4 bandwidth limiter overshoot control , enable warb channel
        M4U_WriteReg32(REG_SMI_READ_FIFO_TH , 0 , 0xC8F);//total 8 commnads between smi common to M4U, 12 non ultra commands between smi common to M4U, 1 commnads can in write AXI slice for all LARBs

        M4U_WriteReg32(REG_SMI_L1ARB0 , 0 , 0xC57);//1111/4096 maximum grant counts, soft limiter
        M4U_WriteReg32(REG_SMI_L1ARB1 , 0 , 0x9F7);//503/4096 maximum grant counts, soft limiter
        M4U_WriteReg32(REG_SMI_L1ARB2 , 0 , 0xD4F);//1359/4096 maximum grant counts, soft limiter
        M4U_WriteReg32(REG_SMI_L1ARB3 , 0 , 0x884912);// 274/4096 maximum grant counts, soft limiter, 2 read 2 write outstanding limit

        M4U_WriteReg32(LARB0_BASE , 0x200 , 0x8);//OVL
        M4U_WriteReg32(LARB0_BASE , 0x204 , 0x8);//RDMA
        M4U_WriteReg32(LARB0_BASE , 0x208 , 0x1);//WDMA
        M4U_WriteReg32(LARB0_BASE , 0x20C , 0x1);//CMDQ
        M4U_WriteReg32(LARB0_BASE , 0x210 , 0x2);//MDP_RDMA
        M4U_WriteReg32(LARB0_BASE , 0x214 , 0x2);//MDP_WDMA
        M4U_WriteReg32(LARB0_BASE , 0x218 , 0x2);//MDP_ROTO
        M4U_WriteReg32(LARB0_BASE , 0x21C , 0x4);//MDP_ROTCO
        M4U_WriteReg32(LARB0_BASE , 0x220 , 0x1);//MDP_ROTVO

        M4U_WriteReg32(LARB1_BASE , 0x200 , 0x1);//MC
        M4U_WriteReg32(LARB1_BASE , 0x204 , 0x1);//PP
        M4U_WriteReg32(LARB1_BASE , 0x208 , 0x1);//AVC MV
        M4U_WriteReg32(LARB1_BASE , 0x20C , 0x1);//RD
        M4U_WriteReg32(LARB1_BASE , 0x210 , 0x1);//WR
        M4U_WriteReg32(LARB1_BASE , 0x214 , 0x1);//VLD
        M4U_WriteReg32(LARB1_BASE , 0x218 , 0x1);//PPWRAP

        M4U_WriteReg32(LARB2_BASE , 0x200 , 0x6);//IMGO
        M4U_WriteReg32(LARB2_BASE , 0x204 , 0x1);//IMG2O
        M4U_WriteReg32(LARB2_BASE , 0x208 , 0x1);//LSCI
        M4U_WriteReg32(LARB2_BASE , 0x20C , 0x4);//IMGI
        M4U_WriteReg32(LARB2_BASE , 0x210 , 0x1);//ESFKO
        M4U_WriteReg32(LARB2_BASE , 0x214 , 0x1);//AAO
        M4U_WriteReg32(LARB2_BASE , 0x218 , 0x1);//JPG_RDMA
        M4U_WriteReg32(LARB2_BASE , 0x21C , 0x1);//JPG_BSDMA
        M4U_WriteReg32(LARB2_BASE , 0x220 , 0x1);//VENC_RD_COMV
        M4U_WriteReg32(LARB2_BASE , 0x224 , 0x1);//VENC_SV_COMV
        M4U_WriteReg32(LARB2_BASE , 0x228 , 0x1);//VENC_RCPU
        M4U_WriteReg32(LARB2_BASE , 0x22C , 0x2);//VENC_REC_FRM
        M4U_WriteReg32(LARB2_BASE , 0x230 , 0x4);//VENC_REF_LUMA
        M4U_WriteReg32(LARB2_BASE , 0x234 , 0x2);//VENC_REF_CHROMA
        M4U_WriteReg32(LARB2_BASE , 0x238 , 0x1);//VENC_BSDMA
        M4U_WriteReg32(LARB2_BASE , 0x23C , 0x2);//VENC_CUR_LUMA
        M4U_WriteReg32(LARB2_BASE , 0x240 , 0x1);//VENC_CUR_CHROMA

#endif
        break;
        
    case SMI_BWC_SCEN_NORMAL:
        SMIMSG( "[SMI_PROFILE] : %s\n", "SMI_BWC_SCEN_NORMAL");

        initSetting();

    default:
        break;
    }

    /*turn off larb clock*/    
    for(i = 0 ; i < SMI_LARB_NR ; i++){
        larb_clock_off(i);
    }

    spin_unlock(&g_SMIInfo.SMI_lock);

    SMIMSG("ScenTo:%d,turn %s,Curr Scen:%d,%d,%d,%d\n" , p_conf->scenario , (p_conf->b_on_off ? "on" : "off") , eFinalScen , 
        g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VR] , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_VP]);

//Debug usage - S
//smi_dumpDebugMsg();
//SMIMSG("Config:%d,%d,%d\n" , eFinalScen , g_SMIInfo.pu4ConcurrencyTable[SMI_BWC_SCEN_NORMAL] , (NULL == pu4LocalCnt ? (-1) : pu4LocalCnt[p_conf->scenario]));
//Debug usage - E

    return 0;
    
}
Ejemplo n.º 7
0
static int smi_bwc_config( MTK_SMI_BWC_CONFIG* p_conf )
{

    int i;
    unsigned wdata = 0;
    unsigned threshold = 0;
    unsigned int larb_base = gLarbBaseAddr[0];

    /*turn on larb clock*/    
    for(i=0; i<SMI_LARB_NR; i++){
        larb_clock_on(i, "SMI");
    }

    /*Bandwidth Limiter*/
    switch( p_conf->scenario )
    {
#if 0    
    case SMI_BWC_SCEN_VP1066:
        wdata = 391; //BW limit = x/4096
        wdata |= (1<<11); // bw filter enable
        wdata |= (1<<12); // bw hard limit enable		
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );   
        wdata = 1494; //BW limit 
        wdata |= (1<<11); // bw filter enable, soft mode
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, wdata ); 

        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0xfffff );		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x00, 0x4 );
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x04, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x08, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x10, 0x1 ); 	
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x14, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x18, 0x2 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x1c, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x20, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x24, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x28, 0x1 );		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x2c, 0x1 );
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x30, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x34, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x38, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x3c, 0x1 ); 

        break;
#endif        
    case SMI_BWC_SCEN_VR1066:
        SMIMSG("set as SMI_BWC_SCEN_VR1066");		
#if 0
        wdata = 432; //BW limit = x/4096
        wdata |= (1<<11); // bw filter enable
        wdata |= (1<<12); // bw hard limit enable		
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata );   
#else
        wdata = 0;   
        threshold = 7;
        wdata |= (1<<12); // bw hard limit enable		
        wdata |= (threshold<<13);
        wdata |= (threshold<<18);
        wdata |= (1<<23);
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, wdata ); 
#endif

        wdata = 2026; //BW limit 
        wdata |= (1<<11); // bw filter enable, soft mode
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, wdata ); 

        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0xfffff );		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x00, 0x6 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x04, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x08, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x10, 0x4 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x14, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x18, 0x2 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x1c, 0x3 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x20, 0x1 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x24, 0x3 ); 
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x28, 0x3 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x2c, 0x3 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x30, 0x1 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x34, 0x3 ); 		
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x38, 0x1 ); 				
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_PORT+0x3c, 0x1 ); 						


        /*reduce command buffer*/
        //if( p_conf->b_reduce_command_buffer )
        {
            /*SMI COMMON reduce command buffer*/
            M4U_WriteReg32( 0x0, REG_SMI_L1LEN, 0xb );				
            M4U_WriteReg32( 0x0, REG_SMI_READ_FIFO_TH, 0x323 );
            M4U_WriteReg32( 0x0, REG_SMI_M4U_TH, 0x10c85 );						
             
        }		
		
        break;
        
    case SMI_BWC_SCEN_NORMAL:
    default:
        SMIMSG("set as SMI_BWC_SCEN_NORMAL");				
        M4U_WriteReg32( larb_base, SMI_LARB_OSTD_CTRL_EN, 0x0 );	
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB0, 0x0   );   //larb0 venc:default
        M4U_WriteReg32( 0x0, REG_SMI_L1ARB1, 0x0   );   //larb1 vdec:default

        {
            /*SMI COMMON reduce command buffer*/
            M4U_WriteReg32( 0x0, REG_SMI_L1LEN, 0x3 );				
            M4U_WriteReg32( 0x0, REG_SMI_READ_FIFO_TH, 0x320 );
            M4U_WriteReg32( 0x0, REG_SMI_M4U_TH, 0x29ca7 );						
             
        }	
		
        break;
    }



    #if 0 /*dump message*/
    {
        #define _SMI_BC_DUMP_REG( _base_, _off_ ) \
            SMIMSG( "[SMI_REG] %s + %s = 0x%08X !\n", #_base_, #_off_, M4U_ReadReg32( _base_, _off_ ) );

        /*Bandwidth Limiter*/
        _SMI_BC_DUMP_REG( 0x0, REG_SMI_L1ARB0 );   //larb0 venc
        _SMI_BC_DUMP_REG( 0x0, REG_SMI_L1ARB1 );   //larb1 vdec

        
        /*SMI COMMON reduce command buffer*/
        _SMI_BC_DUMP_REG( 0x0, REG_SMI_L1LEN );
        _SMI_BC_DUMP_REG( 0x0, REG_SMI_READ_FIFO_TH );		
        _SMI_BC_DUMP_REG( 0x0, REG_SMI_M4U_TH );

        _SMI_BC_DUMP_REG( larb_base, SMI_LARB_OSTD_CTRL_EN);

        for(i = 0; i<20; i++)
        {
            _SMI_BC_DUMP_REG( larb_base, SMI_LARB_OSTD_PORT+0x4*i); 
        }
        
        /*SMI LARB reduce command buffer (RO register)*/
        _SMI_BC_DUMP_REG( LARB0_BASE, 0x10 );
    }


    dump_smi_register();
	
    #endif


    /*turn off larb clock*/    
    for(i=0; i<SMI_LARB_NR; i++){
        larb_clock_off(i, "SMI");
    }
    return 0;
    
}