__s32 BSP_disp_tv_open(__u32 sel) { if((!(gdisp.screen[sel].status & TV_ON))) { __disp_tv_mode_t tv_mod; __panel_para_t para; memset(¶, 0, sizeof(__panel_para_t)); tv_mod = gdisp.screen[sel].tv_mode; lcdc_clk_on(sel, 0, 0); disp_clk_cfg(sel, DISP_OUTPUT_TYPE_TV, tv_mod); lcdc_clk_on(sel, 0, 1); drc_clk_open(sel,0); tcon_init(sel); image_clk_on(sel, 1); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit BSP_disp_set_output_csc(sel, DISP_OUT_CSC_TYPE_LCD, BSP_disp_drc_get_input_csc(sel)); //LCD -->GM7121, rgb fmt DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); disp_tv_get_timing(¶, tv_mod); tcon0_cfg(sel,(__panel_para_t*)¶); tcon0_src_select(sel,4); if(gdisp.screen[sel].tv_ops.tv_power_on) { gdisp.screen[sel].tv_ops.tv_power_on(1); msleep(500); } disp_tv_pin_cfg(1); tcon0_open(sel,(__panel_para_t*)¶); if(gdisp.screen[sel].tv_ops.tv_open) { gdisp.screen[sel].tv_ops.tv_open(); } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status = TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON0_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_LCD;//LCD -->GM7121, rgb fmt if(BSP_disp_cmu_get_enable(sel) ==1) { IEP_CMU_Set_Imgsize(sel, BSP_disp_get_screen_width(sel), BSP_disp_get_screen_height(sel)); } Disp_set_out_interlace(sel); #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif tcon0_src_select(sel,0); } return DIS_SUCCESS; }
__s32 BSP_disp_hdmi_open(__u32 sel) { if(!(gdisp.screen[sel].status & HDMI_ON)) { __disp_tv_mode_t tv_mod; __u32 scaler_index; tv_mod = gdisp.screen[sel].hdmi_mode; hdmi_clk_on(); lcdc_clk_on(sel); image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(sel,DISP_OUTPUT_TYPE_HDMI, tv_mod); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_HDMI); DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); DE_BE_Set_Outitl_enable(sel, Disp_get_screen_scan_mode(tv_mod)); for(scaler_index=0; scaler_index<2; scaler_index++) { if((gdisp.scaler[scaler_index].status & SCALER_USED) && (gdisp.scaler[scaler_index].screen_index == sel)) { if(Disp_get_screen_scan_mode(tv_mod) == 1)//interlace output { Scaler_Set_Outitl(scaler_index, TRUE); } else { Scaler_Set_Outitl(scaler_index, FALSE); } } } TCON1_set_hdmi_mode(sel,tv_mod); TCON1_open(sel); if(gdisp.init_para.Hdmi_open) { gdisp.init_para.Hdmi_open(); } else { DE_WRN("Hdmi_open is NULL\n"); return -1; } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod); gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= HDMI_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_HDMI; #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif } return DIS_SUCCESS; }
__s32 Disp_lcdc_init(__u32 sel) { lcdc_clk_init(sel); lcdc_clk_on(sel); //??need to be open LCDC_init(sel); lcdc_clk_off(sel); Disp_pwm_cfg(sel); if(sel == 0) { LCD_get_panel_funs_0(&lcd_panel_fun[sel]); OSAL_RegISR(INTC_IRQNO_LCDC0,0,Disp_lcdc_event_proc,(void*)sel,0,0); //OSAL_InterruptEnable(INTC_IRQNO_LCDC0); } else { LCD_get_panel_funs_1(&lcd_panel_fun[sel]); OSAL_RegISR(INTC_IRQNO_LCDC1,0,Disp_lcdc_event_proc,(void*)sel,0,0); //OSAL_InterruptEnable(INTC_IRQNO_LCDC1); } lcd_panel_fun[sel].cfg_panel_info(&gpanel_info[sel]); return DIS_SUCCESS; }
__s32 BSP_disp_lcd_open_before(__u32 sel) { disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL); lcdc_clk_on(sel); image_clk_on(sel); /* * set image normal channel start bit, because every de_clk_off( ) * will reset this bit */ Image_open(sel); Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1); if (gpanel_info[sel].tcon_index == 0) TCON0_cfg(sel, (__panel_para_t *) &gpanel_info[sel]); else TCON1_cfg_ex(sel, (__panel_para_t *) &gpanel_info[sel]); #ifdef CONFIG_ARCH_SUN4I BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD); #else BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD, gdisp.screen[sel].iep_status & DRC_USED); #endif DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x, gpanel_info[sel].lcd_y); DE_BE_Output_Select(sel, sel); open_flow[sel].func_num = 0; lcd_panel_fun[sel].cfg_open_flow(sel); return DIS_SUCCESS; }
__s32 BSP_disp_lcd_open_before(__u32 sel) { disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, DIS_NULL); lcdc_clk_on(sel); image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1); if(gpanel_info[sel].tcon_index == 0) { TCON0_cfg(sel,(__panel_para_t*)&gpanel_info[sel]); } else { TCON1_cfg_ex(sel,(__panel_para_t*)&gpanel_info[sel]); } BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_LCD); DE_BE_set_display_size(sel, gpanel_info[sel].lcd_x, gpanel_info[sel].lcd_y); DE_BE_Output_Select(sel, sel); open_flow[sel].func_num = 0; lcd_panel_fun[sel].cfg_open_flow(sel); return DIS_SUCCESS; }
__s32 BSP_disp_tv_open(__u32 sel) { if(!(gdisp.screen[sel].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].tv_mode; image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(); lcdc_clk_on(sel); TCON1_set_tv_mode(sel,tv_mod); TVE_set_tv_mode(sel, tv_mod); Disp_TVEC_DacCfg(sel, tv_mod); TCON1_open(sel); Disp_TVEC_Open(sel); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); gdisp.screen[sel].status |= TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; } return DIS_SUCCESS; }
__s32 bsp_disp_vga_open(__u32 screen_id) { if(!(gdisp.screen[screen_id].status & VGA_ON)) { __disp_vga_mode_t vga_mode; __u32 i = 0; vga_mode = gdisp.screen[screen_id].vga_mode; lcdc_clk_on(screen_id, 1, 0); lcdc_clk_on(screen_id, 1, 1); tcon_init(screen_id); image_clk_on(screen_id, 1); Image_open(screen_id);//set image normal channel start bit , because every de_clk_off( )will reset this bit tve_clk_on(screen_id); disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_VGA, vga_mode); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_VGA; bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); DE_BE_set_display_size(screen_id, vga_mode_to_width(vga_mode), vga_mode_to_height(vga_mode)); DE_BE_Output_Select(screen_id, screen_id); tcon1_set_vga_mode(screen_id,vga_mode); TVE_set_vga_mode(screen_id); Disp_TVEC_Open(screen_id); tcon1_open(screen_id); for(i=0; i<4; i++) { if(gdisp.screen[screen_id].dac_source[i] == DISP_TV_DAC_SRC_COMPOSITE) { TVE_dac_set_source(1-screen_id, i, DISP_TV_DAC_SRC_COMPOSITE); TVE_dac_sel(1-screen_id, i, i); } } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode); gdisp.screen[screen_id].b_out_interlace = 0; gdisp.screen[screen_id].status |= VGA_ON; gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_VGA; #ifdef __LINUX_OSAL__ Display_set_fb_timming(screen_id); #endif } return DIS_SUCCESS; }
__s32 BSP_disp_vga_open(__u32 sel) { if (!(gdisp.screen[sel].status & VGA_ON)) { __disp_vga_mode_t vga_mode; __u32 i = 0; vga_mode = gdisp.screen[sel].vga_mode; lcdc_clk_on(sel); image_clk_on(sel); /* * set image normal channel start bit , because every * de_clk_off( ) will reset this bit */ Image_open(sel); tve_clk_on(sel); disp_clk_cfg(sel, DISP_OUTPUT_TYPE_VGA, vga_mode); Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_VGA, 1); #ifdef CONFIG_ARCH_SUN4I BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA); #else BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_VGA, gdisp.screen[sel]. iep_status & DRC_USED); #endif DE_BE_set_display_size(sel, vga_mode_to_width(vga_mode), vga_mode_to_height(vga_mode)); DE_BE_Output_Select(sel, sel); TCON1_set_vga_mode(sel, vga_mode); TVE_set_vga_mode(sel); Disp_TVEC_Open(sel); TCON1_open(sel); for (i = 0; i < 4; i++) { if (gdisp.screen[sel].dac_source[i] == DISP_TV_DAC_SRC_COMPOSITE) { TVE_dac_set_source(1 - sel, i, DISP_TV_DAC_SRC_COMPOSITE); TVE_dac_sel(1 - sel, i, i); } } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_VGA, vga_mode); gdisp.screen[sel].b_out_interlace = 0; gdisp.screen[sel].status |= VGA_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_VGA; Display_set_fb_timing(sel); } return DIS_SUCCESS; }
__s32 Disp_lcdc_init(__u32 sel) { irqreturn_t ret; LCD_get_sys_config(sel, &(gdisp.screen[sel].lcd_cfg)); lcdc_clk_init(sel); lvds_clk_init(); lcdc_clk_on(sel); /* ??need to be open */ LCDC_init(sel); lcdc_clk_off(sel); if (sel == 0) ret = request_irq(INTC_IRQNO_LCDC0, Disp_lcdc_event_proc, IRQF_DISABLED, "sunxi lcd0", (void *)sel); else ret = request_irq(INTC_IRQNO_LCDC1, Disp_lcdc_event_proc, IRQF_DISABLED, "sunxi lcd1", (void *)sel); if (gdisp.screen[sel].lcd_cfg.lcd_used) { if (lcd_panel_fun[sel].cfg_panel_info) lcd_panel_fun[sel].cfg_panel_info(&gpanel_info[sel]); else LCD_get_panel_para(sel, &gpanel_info[sel]); gpanel_info[sel].tcon_index = 0; if (!sunxi_is_version_A() && (gpanel_info[sel].lcd_pwm_not_used == 0)) { __pwm_info_t pwm_info; pwm_info.enable = 0; pwm_info.active_state = 1; pwm_info.period_ns = 1000000 / gpanel_info[sel].lcd_pwm_freq; if (gpanel_info[sel].lcd_pwm_pol == 0) pwm_info.duty_ns = (gdisp.screen[sel].lcd_cfg.init_bright * pwm_info.period_ns) / 256; else pwm_info.duty_ns = ((256 - gdisp.screen[sel].lcd_cfg.init_bright) * pwm_info.period_ns) / 256; pwm_set_para(gpanel_info[sel].lcd_pwm_ch, &pwm_info); } LCD_GPIO_init(sel); } return DIS_SUCCESS; }
__s32 BSP_disp_lcd_open_before(__u32 sel) { disp_clk_cfg(sel, DISP_OUTPUT_TYPE_LCD, 0); lcdc_clk_on(sel); image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit Disp_lcdc_pin_cfg(sel, DISP_OUTPUT_TYPE_LCD, 1); if(gpanel_info[sel].tcon_index == 0) { TCON0_cfg(sel,(__ebios_panel_para_t*)&gpanel_info[sel]); } else { TCON1_cfg_ex(sel,(__ebios_panel_para_t*)&gpanel_info[sel]); } open_flow[sel].func_num = 0; lcd_panel_fun[sel].cfg_open_flow(sel); return DIS_SUCCESS; }
__s32 bsp_disp_tv_open(__u32 screen_id) { if(!(gdisp.screen[screen_id].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[screen_id].tv_mode; image_clk_on(screen_id, 1); Image_open(screen_id);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(screen_id); lcdc_clk_on(screen_id, 1, 0); lcdc_clk_on(screen_id, 1, 1); tcon_init(screen_id); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_TV; bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); DE_BE_set_display_size(screen_id, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(screen_id, screen_id); #if (defined CONFIG_ARCH_SUN5I) __u32 scaler_index = 0; DE_BE_Set_Outitl_enable(screen_id , disp_get_screen_scan_mode(tv_mod)); for(scaler_index=0; scaler_index<2; scaler_index++) { if((gdisp.scaler[scaler_index].status & SCALER_USED) && (gdisp.scaler[scaler_index].screen_index == screen_id)) { if(disp_get_screen_scan_mode(tv_mod) == 1)//interlace output { Scaler_Set_Outitl(scaler_index, TRUE); } else { Scaler_Set_Outitl(scaler_index, FALSE); } } } #endif tcon1_set_tv_mode(screen_id,tv_mod); TVE_set_tv_mode(screen_id, tv_mod); Disp_TVEC_DacCfg(screen_id, tv_mod); tcon1_open(screen_id); Disp_TVEC_Open(screen_id); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); #ifdef __LINUX_OSAL__ { disp_gpio_set_t gpio_info[1]; __hdle gpio_pa_shutdown; __s32 ret; memset(gpio_info, 0, sizeof(disp_gpio_set_t)); ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(disp_gpio_set_t)/sizeof(int)); if(ret == 0) { gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1); if(!gpio_pa_shutdown) { DE_WRN("audio codec_wakeup request gpio fail!\n"); } else { OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl"); } } } #endif gdisp.screen[screen_id].b_out_interlace = disp_get_screen_scan_mode(tv_mod); gdisp.screen[screen_id].status |= TV_ON; gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_TV; #if (defined CONFIG_ARCH_SUN7I) Disp_set_out_interlace(screen_id); #endif #ifdef __LINUX_OSAL__ Display_set_fb_timming(screen_id); #endif } return DIS_SUCCESS; }
__s32 BSP_disp_tv_open(__u32 sel) { if (!(gdisp.screen[sel].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].tv_mode; image_clk_on(sel); /* * set image normal channel start bit , because every * de_clk_off( )will reset this bit */ Image_open(sel); disp_clk_cfg(sel, DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(sel); lcdc_clk_on(sel); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_TV, gdisp.screen[sel]. iep_status & DRC_USED); DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); if (sunxi_is_sun5i()) { int scaler_index; DE_BE_Set_Outitl_enable(sel, Disp_get_screen_scan_mode(tv_mod)); for (scaler_index = 0; scaler_index < 2; scaler_index++) if ((gdisp.scaler[scaler_index]. status & SCALER_USED) && (gdisp.scaler[scaler_index]. screen_index == sel)) { /* interlace output */ if (Disp_get_screen_scan_mode(tv_mod) == 1) Scaler_Set_Outitl(scaler_index, TRUE); else Scaler_Set_Outitl(scaler_index, FALSE); } } TCON1_set_tv_mode(sel, tv_mod); TVE_set_tv_mode(sel, tv_mod); Disp_TVEC_DacCfg(sel, tv_mod); TCON1_open(sel); Disp_TVEC_Open(sel); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); Disp_de_flicker_enable(sel, TRUE); { user_gpio_set_t gpio_info[1]; __hdle gpio_pa_shutdown; __s32 ret; memset(gpio_info, 0, sizeof(user_gpio_set_t)); ret = script_parser_fetch("audio_para", "audio_pa_ctrl", (int *)gpio_info, sizeof(user_gpio_set_t) / sizeof(int)); if (ret < 0) { DE_WRN("fetch script data " "audio_para.audio_pa_ctrl fail\n"); } else { gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1); if (!gpio_pa_shutdown) { DE_WRN("audio codec_wakeup request " "gpio fail!\n"); } else { OSAL_GPIO_DevWRITE_ONEPIN_DATA (gpio_pa_shutdown, 0, "audio_pa_ctrl"); } } } gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; Disp_set_out_interlace(sel); Display_set_fb_timing(sel); } return DIS_SUCCESS; }
__s32 bsp_disp_hdmi_open(__u32 screen_id) { if(disp_hdmi_get_support(screen_id) && (gdisp.screen[screen_id].hdmi_used) && (!(gdisp.screen[screen_id].status & HDMI_ON))) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[screen_id].hdmi_mode; hdmi_clk_on(); lcdc_clk_on(screen_id, 1, 0); lcdc_clk_on(screen_id, 1, 1); drc_clk_open(screen_id,0); drc_clk_open(screen_id,1); tcon_init(screen_id); image_clk_on(screen_id, 1); /* set image normal channel start bit , because every de_clk_off( )will reset this bit */ Image_open(screen_id); disp_clk_cfg(screen_id,DISP_OUTPUT_TYPE_HDMI, tv_mod); //bsp_disp_set_output_csc(screen_id, DISP_OUTPUT_TYPE_HDMI, gdisp.screen[screen_id].iep_status&DRC_USED); if(gdisp.init_para.hdmi_cts_compatibility == 0) { DE_INF("bsp_disp_hdmi_open: disable dvi mode\n"); bsp_disp_hdmi_dvi_enable(screen_id, 0); } else if(gdisp.init_para.hdmi_cts_compatibility == 1) { DE_INF("bsp_disp_hdmi_open: enable dvi mode\n"); bsp_disp_hdmi_dvi_enable(screen_id, 1); } else { bsp_disp_hdmi_dvi_enable(screen_id, bsp_disp_hdmi_dvi_support(screen_id)); } if(BSP_dsip_hdmi_get_input_csc(screen_id) == 0) { __inf("bsp_disp_hdmi_open: hdmi output rgb\n"); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_RGB; bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); } else { __inf("bsp_disp_hdmi_open: hdmi output yuv\n"); gdisp.screen[screen_id].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_YUV;//default yuv bsp_disp_set_output_csc(screen_id, gdisp.screen[screen_id].output_csc_type, bsp_disp_drc_get_input_csc(screen_id)); } DE_BE_set_display_size(screen_id, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(screen_id, screen_id); bsp_disp_hdmi_set_src(screen_id, DISP_LCDC_SRC_DE_CH1); tcon1_set_hdmi_mode(screen_id,tv_mod); tcon1_open(screen_id); if(gdisp.init_para.hdmi_open) { gdisp.init_para.hdmi_open(); } else { DE_WRN("Hdmi_open is NULL\n"); return -1; } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod); gdisp.screen[screen_id].b_out_interlace = disp_get_screen_scan_mode(tv_mod); gdisp.screen[screen_id].status |= HDMI_ON; gdisp.screen[screen_id].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[screen_id].output_type = DISP_OUTPUT_TYPE_HDMI; if(bsp_disp_cmu_get_enable(screen_id) ==1) { IEP_CMU_Set_Imgsize(screen_id, bsp_disp_get_screen_width(screen_id), bsp_disp_get_screen_height(screen_id)); } Disp_set_out_interlace(screen_id); #ifdef __LINUX_OSAL__ Display_set_fb_timming(screen_id); #endif return DIS_SUCCESS; } return DIS_NOT_SUPPORT; }
__s32 BSP_disp_tv_open(__u32 sel) { if(!(gdisp.screen[sel].status & TV_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].tv_mode; image_clk_on(sel); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit disp_clk_cfg(sel,DISP_OUTPUT_TYPE_TV, tv_mod); tve_clk_on(sel); lcdc_clk_on(sel); BSP_disp_set_output_csc(sel, DISP_OUTPUT_TYPE_TV); DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); TCON1_set_tv_mode(sel,tv_mod); TVE_set_tv_mode(sel, tv_mod); Disp_TVEC_DacCfg(sel, tv_mod); TCON1_open(sel); Disp_TVEC_Open(sel); Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_TV, tv_mod); #ifdef __LINUX_OSAL__ { user_gpio_set_t gpio_info[1]; __hdle gpio_pa_shutdown; __s32 ret; memset(gpio_info, 0, sizeof(user_gpio_set_t)); ret = OSAL_Script_FetchParser_Data("audio_para","audio_pa_ctrl", (int *)gpio_info, sizeof(user_gpio_set_t)/sizeof(int)); if(ret < 0) { DE_WRN("fetch script data audio_para.audio_pa_ctrl fail\n"); } else { gpio_pa_shutdown = OSAL_GPIO_Request(gpio_info, 1); if(!gpio_pa_shutdown) { DE_WRN("audio codec_wakeup request gpio fail!\n"); } else { OSAL_GPIO_DevWRITE_ONEPIN_DATA(gpio_pa_shutdown, 0, "audio_pa_ctrl"); } } } #endif gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= TV_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_TV; Disp_set_out_interlace(sel); #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif } return DIS_SUCCESS; }
__s32 Disp_lcdc_init(__u32 sel) { LCD_get_sys_config(sel, &(gdisp.screen[sel].lcd_cfg)); lcdc_clk_init(sel); lvds_clk_init(); lcdc_clk_on(sel); //??need to be open LCDC_init(sel); lcdc_clk_off(sel); if(sel == 0) { OSAL_RegISR(INTC_IRQNO_LCDC0,0,Disp_lcdc_event_proc,(void*)sel,0,0); #ifndef __LINUX_OSAL__ OSAL_InterruptEnable(INTC_IRQNO_LCDC0); LCD_get_panel_funs_0(&lcd_panel_fun[sel]); #endif } else { OSAL_RegISR(INTC_IRQNO_LCDC1,0,Disp_lcdc_event_proc,(void*)sel,0,0); #ifndef __LINUX_OSAL__ OSAL_InterruptEnable(INTC_IRQNO_LCDC1); LCD_get_panel_funs_1(&lcd_panel_fun[sel]); #endif } if(gdisp.screen[sel].lcd_cfg.lcd_used) { if(lcd_panel_fun[sel].cfg_panel_info) { lcd_panel_fun[sel].cfg_panel_info(&gpanel_info[sel]); } else { LCD_get_panel_para(sel, &gpanel_info[sel]); } gpanel_info[sel].tcon_index = 0; if((OSAL_sw_get_ic_ver() != 0xA) && (gpanel_info[sel].lcd_pwm_not_used == 0)) { __pwm_info_t pwm_info; pwm_info.enable = 0; pwm_info.active_state = 1; pwm_info.period_ns = 1000000 / gpanel_info[sel].lcd_pwm_freq; if(gpanel_info[sel].lcd_pwm_pol == 0) { pwm_info.duty_ns = (192 * pwm_info.period_ns) / 256; } else { pwm_info.duty_ns = ((256 - 192) * pwm_info.period_ns) / 256; } pwm_set_para(gpanel_info[sel].lcd_pwm_ch, &pwm_info); } LCD_GPIO_init(sel); } return DIS_SUCCESS; }
__s32 BSP_disp_hdmi_open(__u32 sel) { if(!(gdisp.screen[sel].status & HDMI_ON)) { __disp_tv_mode_t tv_mod; tv_mod = gdisp.screen[sel].hdmi_mode; BSP_disp_hdmi_get_hdcp_enable(); hdmi_clk_on(); if(gdisp.screen[sel].hdmi_hdcp_en) hdcp_clk_init(tv_mod); lcdc_clk_on(sel, 1, 0); lcdc_clk_on(sel, 1, 1); Disp_lcdc_reg_isr(sel); LCDC_init(sel); image_clk_on(sel, 0); image_clk_on(sel, 1); Image_open(sel);//set image normal channel start bit , because every de_clk_off( )will reset this bit DE_BE_EnableINT(sel, DE_IMG_REG_LOAD_FINISH); disp_clk_cfg(sel,DISP_OUTPUT_TYPE_HDMI, tv_mod); if(gdisp.init_para.hdmi_cts_compatibility == 0) { DE_INF("BSP_disp_hdmi_open: disable dvi mode\n"); BSP_disp_hdmi_dvi_enable(sel, 0); } else if(gdisp.init_para.hdmi_cts_compatibility == 1) { DE_INF("BSP_disp_hdmi_open: enable dvi mode\n"); BSP_disp_hdmi_dvi_enable(sel, 1); } else { BSP_disp_hdmi_dvi_enable(sel, BSP_disp_hdmi_dvi_support(sel)); } if(BSP_dsip_hdmi_get_input_csc(sel) == 0) { __inf("BSP_disp_hdmi_open: hdmi output rgb\n"); gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_RGB; BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type); }else { __inf("BSP_disp_hdmi_open: hdmi output yuv\n"); gdisp.screen[sel].output_csc_type = DISP_OUT_CSC_TYPE_HDMI_YUV;//default yuv BSP_disp_set_output_csc(sel, gdisp.screen[sel].output_csc_type); } DE_BE_set_display_size(sel, tv_mode_to_width(tv_mod), tv_mode_to_height(tv_mod)); DE_BE_Output_Select(sel, sel); tcon1_set_hdmi_mode(sel,tv_mod); tcon1_open(sel); if(gdisp.init_para.hdmi_open) { gdisp.init_para.hdmi_open(); } else { DE_WRN("hdmi_open is NULL\n"); return -1; } Disp_Switch_Dram_Mode(DISP_OUTPUT_TYPE_HDMI, tv_mod); gdisp.screen[sel].b_out_interlace = Disp_get_screen_scan_mode(tv_mod); gdisp.screen[sel].status |= HDMI_ON; gdisp.screen[sel].lcdc_status |= LCDC_TCON1_USED; gdisp.screen[sel].output_type = DISP_OUTPUT_TYPE_HDMI; Disp_set_out_interlace(sel); #ifdef __LINUX_OSAL__ Display_set_fb_timming(sel); #endif } return DIS_SUCCESS; }