static void a1x_dumpintc(const char *msg, int irq)
{
irqstate_t flags;
flags = irqsave();
lldbg("INTC (%s, irq=%d):\n", msg, irq);
/* Select the register set associated with this irq */
putreg32(irq, A1X_INTC_SSR);
/* Then dump all of the (readable) register contents */
lldbg(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
lldbg(" IRQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
getreg32(A1X_INTC_IRQ_PEND2));
lldbg(" FIQ PEND: %08x %08x %08x\n",
getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
getreg32(A1X_INTC_FIQ_PEND2));
lldbg(" SEL: %08x %08x %08x\n",
getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
getreg32(A1X_INTC_IRQ_SEL2));
lldbg(" EN: %08x %08x %08x\n",
getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
getreg32(A1X_INTC_EN2));
lldbg(" MASK: %08x %08x %08x\n",
getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
getreg32(A1X_INTC_MASK2));
lldbg(" RESP: %08x %08x %08x\n",
getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
getreg32(A1X_INTC_RESP2));
lldbg(" FF: %08x %08x %08x\n",
getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
getreg32(A1X_INTC_FF2));
lldbg(" PRIO: %08x %08x %08x %08x %08x\n",
getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
getreg32(A1X_INTC_PRIO4));
irqrestore(flags);
}
static uint32_t *sam_spurious(int irq, uint32_t *regs)
{
/* This is probably irrevelant since true vectored interrupts are not used
* in this implementation. The value of AIC_IVR is ignored.
*/
#if defined(CONFIG_DEBUG_IRQ)
lldbg("Spurious interrupt: IRQ %d\n", irq);
#endif
return regs;
}
/**
* @brief Register a driver with the unipro core
* @param drv unipro driver to register
* @param cportid cport number to associate this driver to
* @return 0 on success, <0 on error
*/
int unipro_driver_register(struct unipro_driver *driver, unsigned int cportid)
{
struct cport *cport = cport_handle(cportid);
if (!cport) {
return -ENODEV;
}
if (cport->driver) {
lldbg("ERROR: Already registered by: %s\n",
cport->driver->name);
return -EEXIST;
}
cport->driver = driver;
lldbg("Registered driver %s on %sconnected CP%u\n",
cport->driver->name, cport->connected ? "" : "un",
cport->cportid);
return 0;
}
int up_memfault(int irq, FAR void *context)
{
/* Dump some memory management fault info */
(void)irqsave();
lldbg("PANIC!!! Memory Management Fault:\n");
mfdbg(" IRQ: %d context: %p\n", irq, regs);
lldbg(" CFAULTS: %08x MMFAR: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
mfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
getbasepri(), getprimask(), getipsr(), getcontrol());
mfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
mfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
# ifdef REG_EXC_RETURN
mfdbg(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
current_regs[REG_XPSR], current_regs[REG_BASEPRI],
current_regs[REG_EXC_RETURN]);
# else
mfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n",
current_regs[REG_XPSR], current_regs[REG_BASEPRI]);
# endif
#else
# ifdef REG_EXC_RETURN
mfdbg(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
current_regs[REG_XPSR], current_regs[REG_PRIMASK],
current_regs[REG_EXC_RETURN]);
# else
mfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
current_regs[REG_XPSR], current_regs[REG_PRIMASK]);
# endif
#endif
PANIC();
return OK; /* Won't get here */
}
static uint32_t *sam_fiqhandler(int irq, uint32_t *regs)
{
/* This is probably irrevelant since FIQs are not used in this
* implementation.
*/
#if defined(CONFIG_DEBUG_IRQ) || defined(CONFIG_ARCH_STACKDUMP)
lldbg("FIQ?: IRQ: %d\n");
#endif
PANIC();
return regs; /* Won't get here */
}
void stm32_gpio_deinit(void)
{
if (!stm32_gpio_chip_initalized) {
lldbg("%s: not initialized, exiting\n", __func__);
return;
}
/* Unregister to gpio_chip */
unregister_gpio_chip(&stm32_gpio_ops);
stm32_gpio_chip_initalized = false;
}
static void stm32_gpio_set_direction_in(void *driver_data, uint8_t pin)
{
uint32_t cfgset;
int ret;
lldbg("%s: pin=%hhu\n", __func__, pin);
ret = map_pin_nr_to_cfgset(pin, &cfgset);
if (ret) {
lldbg("%s: Invalid pin %hhu\n", pin);
return;
}
// Configure pin as input, floating
cfgset |= GPIO_INPUT | GPIO_FLOAT;
lldbg("cfgset=0x%x\n", cfgset);
ret = stm32_configgpio(cfgset);
if (ret)
lldbg("%s: stm32_configgpio returns %d\n", ret);
}
void up_assert(void)
#endif
{
#if CONFIG_TASK_NAME_SIZE > 0
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_HAVE_FILENAME
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
lldbg("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
#else
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed: task: %s\n", rtcb->name);
#else
lldbg("Assertion failed\n");
#endif
#endif
up_stackdump();
up_registerdump();
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
#endif
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), this_task(), filename, lineno);
#endif
_up_assert(EXIT_FAILURE);
}
static void sam_dumpaic(const char *msg, int irq)
{
irqstate_t flags;
flags = irqsave();
lldbg("AIC (%s, irq=%d):\n", msg, irq);
/* Select the register set associated with this irq */
putreg32(irq, SAM_AIC_SSR);
/* Then dump all of the (readable) register contents */
lldbg(" SSR: %08x SMR: %08x SVR: %08x IVR: %08x\n",
getreg32(SAM_AIC_SSR), getreg32(SAM_AIC_SMR),
getreg32(SAM_AIC_SVR), getreg32(SAM_AIC_IVR));
lldbg(" FVR: %08x ISR: %08x\n",
getreg32(SAM_AIC_FVR), getreg32(SAM_AIC_ISR));
lldbg(" IPR: %08x %08x %08x %08x\n",
getreg32(SAM_AIC_IPR0), getreg32(SAM_AIC_IPR1),
getreg32(SAM_AIC_IPR2), getreg32(SAM_AIC_IPR3));
lldbg(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
getreg32(SAM_AIC_IMR), getreg32(SAM_AIC_CISR),
getreg32(SAM_AIC_SPU), getreg32(SAM_AIC_FFSR));
lldbg(" DCR: %08x WPMR: %08x WPMR: %08x\n",
getreg32(SAM_AIC_DCR), getreg32(SAM_AIC_WPMR),
getreg32(SAM_AIC_WPMR));
irqrestore(flags);
}
static void efm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = irqsave();
lldbg("NVIC (%s, irq=%d):\n", msg, irq);
lldbg(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
lldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE));
lldbg(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
lldbg(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
lldbg(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
lldbg(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
#endif
#endif
#endif
irqrestore(flags);
}
static void up_stackdump(uint16_t sp, uint16_t stack_base)
{
uint16_t stack;
for (stack = sp; stack < stack_base; stack += 16)
{
uint8_t *ptr = (uint8_t*)stack;
lldbg("%04x: %02x %02x %02x %02x %02x %02x %02x %02x"
" %02x %02x %02x %02x %02x %02x %02x %02x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5], ptr[6], ptr[7],
ptr[8], ptr[9], ptr[10], ptr[11], ptr[12], ptr[13], ptr[14], ptr[15]);
}
}
int unipro_driver_register(struct unipro_driver *drv, unsigned int cportid) {
lldbg("Registering driver %s on cport: %u\n", drv->name, cportid);
/*
* Only cports 4 and 5 are supported on ES2 silicon
*/
switch (cportid) {
case 4:
case 5:
break;
default:
return -EINVAL;
}
if (g_drvs[cportid]) {
return -EADDRINUSE;
}
g_drvs[cportid] = drv;
lldbg("Registered driver %s on cport: %u\n", drv->name, cportid);
return 0;
}
/**
* @brief Engage camera capture operation
*
* It tell camera module to start capture.
*
* @param operation pointer to structure of Greybus operation message
* @return GB_OP_SUCCESS on success, error code on failure
*/
static uint8_t gb_camera_capture(struct gb_operation *operation)
{
struct gb_camera_capture_request *request;
struct capture_info *capt_req;
size_t request_size;
int ret;
lldbg("gb_camera_capture() + \n");
if (info->state != STATE_CONFIGURED && info->state != STATE_STREAMING) {
return GB_OP_INVALID;
}
request_size = gb_operation_get_request_payload_size(operation);
if (request_size < sizeof(*request)) {
gb_error("dropping short message\n");
return GB_OP_INVALID;
}
request = gb_operation_get_request_payload(operation);
if (request->padding != 0) {
gb_error("invalid padding value\n");
return GB_OP_INVALID;
}
capt_req = malloc(sizeof(*capt_req));
if(!capt_req) {
return GB_OP_NO_MEMORY;
}
capt_req->request_id = le32_to_cpu(request->request_id);
capt_req->streams = request->streams;
capt_req->num_frames = le32_to_cpu(request->num_frames);
capt_req->settings = request->settings;
capt_req->settings_size = request_size - sizeof(*request);
lldbg(" request_id = %d \n", capt_req->request_id);
lldbg(" streams = %d \n", capt_req->streams);
lldbg(" num_frames = %d \n", capt_req->num_frames);
lldbg(" settings_size = %u\n", capt_req->settings_size);
ret = device_camera_capture(info->dev, capt_req);
if (ret) {
gb_error("error in camera capture thread. \n");
ret = gb_errno_to_op_result(ret);
goto err_free_mem;
}
free(capt_req);
lldbg("gb_camera_capture() - \n");
return GB_OP_SUCCESS;
err_free_mem:
free(capt_req);
return ret;
}
static enum svc_state svc_wf_mod__mod_detected(struct svc *svc, struct svc_work *work) {
vdbg("\n");
svc_delete_timer(g_svc.mod_detect_tid);
g_svc.mod_detect_tid = SVC_TIMER_INVALID;
if (g_svc.gearbox) {
gearbox_link_up(g_svc.gearbox);
}
#if defined(CONFIG_ARCH_CHIP_TSB_I2S_TUNNEL)
(void)i2s_unipro_tunnel_unipro_register();
#endif
#if CONFIG_UNIPRO_TEST_CPORTS
# ifdef CONFIG_UNIPRO_TEST_0_CPORT_ID
lldbg("setup cport=%d\n", CONFIG_UNIPRO_TEST_0_CPORT_ID);
unipro_p2p_setup_test_connection(CONFIG_UNIPRO_TEST_0_CPORT_ID,
0 /* test port */, 1 /* APBA to ABPE */, 1 /* E2EFC */);
# endif
# ifdef CONFIG_UNIPRO_TEST_1_CPORT_ID
lldbg("setup cport=%d\n", CONFIG_UNIPRO_TEST_1_CPORT_ID);
unipro_p2p_setup_test_connection(CONFIG_UNIPRO_TEST_1_CPORT_ID,
1 /* test port */, 0 /* APBE to APBA */, 1 /* E2EFC */);
# endif
#endif
#if CONFIG_MHB_IPC_SERVER || CONFIG_MHB_IPC_CLIENT
ipc_register_unipro();
#endif
#if CONFIG_RAMLOG_SYSLOG
mhb_ramlog_enable();
#endif
mhb_send_pm_status_not(MHB_PM_STATUS_PEER_CONNECTED);
mhb_send_id_not();
return SVC_CONNECTED;
}
static int es2_tsb_unipro_set_init_status(uint32_t val)
{
int rc;
rc = unipro_attr_local_write(T_TSTSRCINCREMENT, ES2_INIT_STATUS(val),
UNIPRO_SELINDEX_NULL);
if (rc) {
lldbg("init-status write failed: rc=%d\n", rc);
return rc;
}
return 0;
}
/**
* Since the switch has no 32-bit MBOX_ACK_ATTR attribute, we need to repurpose
* a 16-bit attribute, which means that received mbox values must fit inside a
* uint16_t.
*/
static int tsb_unipro_mbox_ack(uint16_t val) {
int rc;
uint32_t mbox_ack_attr = tsb_get_rev_id() == tsb_rev_es2 ?
ES2_MBOX_ACK_ATTR : ES3_MBOX_ACK_ATTR;
rc = unipro_attr_local_write(mbox_ack_attr, val, 0);
if (rc) {
lldbg("MBOX_ACK_ATTR complement write of 0x%x failed: %d\n", val, rc);
return rc;
}
return 0;
}
static int stm32_gpio_mask_irq(void *driver_data, uint8_t pin)
{
uint32_t cfgset;
int ret = 0;
lldbg("%s: pin=%hhu\n", __func__, pin);
ret = map_pin_nr_to_cfgset(pin, &cfgset);
if (ret) {
lldbg("%s: Invalid pin %hhu\n", pin);
return ret;
}
/* Mask interrupt */
stm32_gpiosetevent_priv(cfgset,
false,
false,
true,
(xcpt_priv_t) stm32_gpio[pin].isr,
NULL);
return ret;
}
static int tfa9890_modify(FAR struct tfa9890_dev_s *priv, uint16_t reg,
uint16_t mask, uint16_t s, uint16_t offset)
{
int val = tfa9890_reg_read(priv, reg);
if (val < 0)
{
lldbg("reg_read failed for 0x%02x rv = %d\n", reg, val);
return val;
}
val = SETBITS(val, mask << offset, s << offset);
return tfa9890_reg_write(priv, reg, val);
}
int unipro_tx_init(void)
{
int retval;
sem_init(&worker.tx_fifo_lock, 0, 0);
retval = pthread_create(&worker.thread, NULL, unipro_tx_worker, NULL);
if (retval) {
lldbg("Failed to create worker thread: %s.\n", strerror(errno));
return retval;
}
return 0;
}
static int stm32_gpio_unmask_irq(void *driver_data, uint8_t pin)
{
uint32_t cfgset;
int ret = 0;
lldbg("%s: pin=%hhu\n", __func__, pin);
ret = map_pin_nr_to_cfgset(pin, &cfgset);
if (ret) {
lldbg("%s: Invalid pin %hhu\n", pin);
return ret;
}
/* Re-install handler */
stm32_gpiosetevent_priv(cfgset,
stm32_gpio[pin].flags & STM32_GPIO_FLAG_RISING,
stm32_gpio[pin].flags & STM32_GPIO_FLAG_FALLING,
true,
(xcpt_priv_t) stm32_gpio[pin].isr,
NULL);
return ret;
}
int tsb_dma_irq_handler(int irq, void *context)
{
volatile tsb_dma_gdmac_control_regs *control_regs =
(tsb_dma_gdmac_control_regs*) GDMAC_CONTROL_REGS_ADDRESS;
unsigned int channel = IRQN_TO_DMA_CHANNEL(irq);
(void) context;
if (channel != DEVICE_DMA_INVALID_CHANNEL) {
control_regs->intclr = GDMAC_EVENT_MASK(channel);
if (tsb_dma_gdmac_dev == NULL) {
lldbg ("Invalid device handle.\n");
} else {
struct tsb_dma_info *info = device_get_private (tsb_dma_gdmac_dev);
sem_post (&info->dma_channel[channel].channel_info->unipro_tx_channel.tx_sem);
}
} else {
lldbg ("received invalid DMA interrupt(%d)\n", irq);
}
return OK;
}
int up_hardfault(int irq, FAR void *context)
{
uint32_t *regs = (uint32_t*)context;
uint16_t *pc;
uint16_t insn;
/* Get the value of the program counter where the fault occurred */
pc = (uint16_t*)regs[REG_PC] - 1;
if ((void*)pc >= (void*)&_stext && (void*)pc < (void*)&_etext)
{
/* Fetch the instruction that caused the Hard fault */
insn = *pc;
hfdbg(" PC: %p INSN: %04x\n", pc, insn);
/* If this was the instruction 'svc 0', then forward processing
* to the SVCall handler
*/
if (insn == INSN_SVC0)
{
hfdbg("Forward SVCall\n");
return up_svcall(irq, context);
}
}
/* Dump some hard fault info */
hfdbg("\nHard Fault:\n");
hfdbg(" IRQ: %d regs: %p\n", irq, regs);
hfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x\n",
getbasepri(), getprimask(), getipsr());
hfdbg(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
getreg32(NVIC_AFAULTS));
hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
hfdbg(" PSR=%08x\n", regs[REG_XPSR]);
(void)irqsave();
lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
PANIC(OSERR_UNEXPECTEDISR);
return OK;
}
/**
* @brief Get Camera capabilities
*
* This operation retrieves the list of capabilities of the Camera Module and
* then returns to host.
*
* @param operation Pointer to structure of Greybus operation.
* @return GB_OP_SUCCESS on success, error code on failure.
*/
static uint8_t gb_camera_capabilities(struct gb_operation *operation)
{
struct gb_camera_capabilities_response *response;
uint8_t *capabilities;
uint16_t size;
int ret;
lldbg("gb_camera_capabilities() + \n");
if (info->state < STATE_UNCONFIGURED) {
lldbg("state error %d \n", info->state);
return GB_OP_INVALID;
}
ret = device_camera_get_required_size(info->dev, SIZE_CAPABILITIES, &size);
if (ret) {
return gb_errno_to_op_result(ret);
}
response = gb_operation_alloc_response(operation, sizeof(*response) + size);
if (!response) {
return GB_OP_NO_MEMORY;
}
/* camera module capabilities */
ret = device_camera_capabilities(info->dev, &size, capabilities);
if (ret) {
return gb_errno_to_op_result(ret);
}
response->size = cpu_to_le16(size);
memcpy(response->capabilities, &capabilities, size);
lldbg("gb_camera_capabilities() - \n");
return GB_OP_SUCCESS;
}
int lpc17_dumpgpio(lpc17_pinset_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
#if defined(LPC176x)
uint32_t pinsel;
uint32_t pinmode;
#elif defined(LPC178x)
uint32_t iocon;
#endif /* LPC176x */
unsigned int port;
unsigned int pin;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
#if defined(LPC176x)
pinsel = lpc17_pinsel(port, pin);
pinmode = lpc17_pinmode(port, pin);
#elif defined(LPC178x)
iocon = LPC17_IOCON_P(port, pin);
#endif /* LPC176x */
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
lldbg("GPIO%c pin%d (pinset: %08x) -- %s\n",
port + '0', pin, pinset, msg);
#if defined(LPC176x)
lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
pinsel, pinsel ? getreg32(pinsel) : 0,
pinmode, pinmode ? getreg32(pinmode) : 0,
g_odmode[port], getreg32(g_odmode[port]));
#elif defined(LPC178x)
lldbg(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
#endif
base = g_fiobase[port];
lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
base = g_intbase[port];
lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
leave_critical_section(flags);
return OK;
}
void up_assert(void)
#endif
{
#if CONFIG_TASK_NAME_SIZE > 0
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
#ifdef CONFIG_HAVE_FILENAME
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
lldbg("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
#else
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed: task: %s\n", rtcb->name);
#else
lldbg("Assertion failed\n");
#endif
#endif
up_stackdump();
REGISTER_DUMP();
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
#endif
_up_assert(EXIT_FAILURE);
}
static inline void hcs12_mebidump(uint8_t portndx)
{
const struct gpio_mebiinfo_s *ptr;
if (portndx >= HCS12_MEBI_NPORTS)
{
lldbg(" Illegal MEBI port index: %d\n", portndx);
return;
}
ptr = &mebiinfo[portndx];
lldbg(" MEBI Port%c:\n", ptr->name);
switch (ptr->form)
{
case MEBIPORT_AB:
lldbg(" DATA:%02x DDR:%02x\n",
getreg8(ptr->data), getreg8(ptr->ddr));
break;
case MEBIPORT_E:
lldbg(" DATA:%02x DDR:%02x MODE:%02x PEAR:%02x\n",
getreg8(ptr->data), getreg8(ptr->ddr),
getreg8(HCS12_MEBI_MODE), getreg8(HCS12_MEBI_PEAR));
break;
case MEBIPORT_K:
lldbg(" DATA:%02x DDR:%02x MODE:%02x\n",
getreg8(ptr->data), getreg8(ptr->ddr),
getreg8(HCS12_MEBI_MODE));
break;
default:
break;
}
}
/**
* @brief print TIME_SYNC debug metrics
*
* Note this thread exists in-lieu of a hardware timer based
* solution - considered to be a WIP and not a real-time solution
*/
static int timesync_debugd_main(int argc, char **argv) {
(void)argc;
(void)argv;
uint8_t i;
while (timesync_state != TIMESYNC_STATE_INVALID) {
/* Don't block when in the active debug state */
if (timesync_state != TIMESYNC_STATE_DEBUG_ACTIVE)
sem_wait(&dbg_thread_sem);
if (timesync_state == TIMESYNC_STATE_INVALID)
break;
switch (timesync_state) {
case TIMESYNC_STATE_DEBUG_ACTIVE:
lldbg("frame-time %llu\n",
timesync_get_frame_time());
sleep(1);
break;
case TIMESYNC_STATE_DEBUG_INIT:
for (i = 1; i < timesync_strobe_index; i++) {
lldbg("frame-time diff %llu-useconds %llu-%llu counter-diff is %llu %llu-%llu\n",
timesync_strobe_time[i] - timesync_strobe_time[i-1],
timesync_strobe_time[i], timesync_strobe_time[i-1],
timesync_strobe_time_counter[i] - timesync_strobe_time_counter[i - 1],
timesync_strobe_time_counter[i], timesync_strobe_time_counter[i - 1]);
}
timesync_set_state(TIMESYNC_STATE_DEBUG_ACTIVE);
break;
default:
break;
}
}
return 0;
}
void up_assert(const uint8_t *filename, int lineno)
{
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
lldbg("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
up_dumpstate();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), this_task(), filename, lineno);
#endif
_up_assert(EXIT_FAILURE);
}
uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
{
/* Save the saved processor context in current_regs where it can be accessed
* for register dumps and possibly context switching.
*/
current_regs = regs;
/* Crash -- possibly showing diagnostic debug information. */
lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
}
/**
* @brief send data over given UniPro CPort
* @return 0 on success, -EINVAL on invalid parameter,
* -EBUSY when buffer could not be completely transferred
* (unipro_send_tx_buffer() shall be called again until
* buffer is entirely sent (return value == 0)).
* @param[in] operation: greybus loopback operation
*/
static int unipro_send_tx_buffer(struct cport *cport)
{
irqstate_t flags;
struct unipro_buffer *buffer;
int retval;
if (!cport) {
return -EINVAL;
}
flags = irqsave();
if (list_is_empty(&cport->tx_fifo)) {
if (cport->pending_reset) {
unipro_flush_cport(cport);
}
irqrestore(flags);
return 0;
}
buffer = list_entry(cport->tx_fifo.next, struct unipro_buffer, list);
irqrestore(flags);
if (cport->pending_reset) {
unipro_flush_cport(cport);
}
retval = unipro_send_sync(cport->cportid,
buffer->data + buffer->byte_sent,
buffer->len - buffer->byte_sent, buffer->som);
if (retval < 0) {
unipro_dequeue_tx_buffer(buffer, retval);
lldbg("unipro_send_sync failed. Dropping message...\n");
return -EINVAL;
}
buffer->som = false;
buffer->byte_sent += retval;
if (buffer->byte_sent >= buffer->len) {
unipro_set_eom_flag(cport);
unipro_dequeue_tx_buffer(buffer, 0);
return 0;
}
return -EBUSY;
}