static void
lmc_ds3_init(lmc_softc_t * const sc)
{
int i;
sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5245;
/* writes zeros everywhere */
for (i = 0 ; i < 21 ; i++) {
lmc_mii_writereg(sc, 0, 17, i);
lmc_mii_writereg(sc, 0, 18, 0);
}
/* set some essential bits */
lmc_mii_writereg(sc, 0, 17, 1);
lmc_mii_writereg(sc, 0, 18, 0x05); /* ser, xtx */
lmc_mii_writereg(sc, 0, 17, 5);
lmc_mii_writereg(sc, 0, 18, 0x80); /* emode */
lmc_mii_writereg(sc, 0, 17, 14);
lmc_mii_writereg(sc, 0, 18, 0x30); /* rcgen, tcgen */
/* clear counters and latched bits */
for (i = 0 ; i < 21 ; i++) {
lmc_mii_writereg(sc, 0, 17, i);
lmc_mii_readreg(sc, 0, 18);
}
}
static void
lmc_hssi_set_link_status(lmc_softc_t * const sc, int state)
{
if (state == LMC_LINK_UP)
sc->lmc_miireg16 |= LMC_MII16_HSSI_TA;
else
sc->lmc_miireg16 &= ~LMC_MII16_HSSI_TA;
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
void
lmc_reset(lmc_softc_t * const sc)
{
sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
/*
* make some of the GPIO pins be outputs
*/
lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
/*
* drive DP and RESET low to force configuration. This also forces
* the transmitter clock to be internal, but we expect to reset
* that later anyway.
*/
sc->lmc_gpio &= ~(LMC_GEP_DP | LMC_GEP_RESET);
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
/*
* hold for more than 10 microseconds
*/
DELAY(50);
/*
* stop driving Xilinx-related signals
*/
lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
/*
* busy wait for the chip to reset
*/
while ((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0);
/*
* Call media specific init routine
*/
sc->lmc_media->init(sc);
}
/*
* 1 == T1 Circuit Type , 0 == E1 Circuit Type
*/
static void
lmc_t1_set_circuit_type(lmc_softc_t * const sc, int ie)
{
if (ie == LMC_CTL_CIRCUIT_TYPE_T1)
{
sc->lmc_miireg16 |= LMC_MII16_T1_Z;
sc->ictl.circuit_type = LMC_CTL_CIRCUIT_TYPE_T1;
} else { sc->lmc_miireg16 &= ~LMC_MII16_T1_Z;
sc->ictl.scrambler_onoff = LMC_CTL_CIRCUIT_TYPE_E1;
}
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
/*
* 1 == DS3 payload scrambled, 0 == not scrambled
*/
static void
lmc_ds3_set_scram(lmc_softc_t * const sc, int ie)
{
if (ie == LMC_CTL_ON) {
sc->lmc_miireg16 |= LMC_MII16_DS3_SCRAM;
sc->ictl.scrambler_onoff = LMC_CTL_ON;
} else {
sc->lmc_miireg16 &= ~LMC_MII16_DS3_SCRAM;
sc->ictl.scrambler_onoff = LMC_CTL_OFF;
}
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
/*
* Set cable length
*/
static void
lmc_ds3_set_100ft(lmc_softc_t * const sc, int ie)
{
if (ie == LMC_CTL_CABLE_LENGTH_GT_100FT) {
sc->lmc_miireg16 &= ~LMC_MII16_DS3_ZERO;
sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_GT_100FT;
} else if (ie == LMC_CTL_CABLE_LENGTH_LT_100FT) {
sc->lmc_miireg16 |= LMC_MII16_DS3_ZERO;
sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_LT_100FT;
}
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
/*
* return hardware link status.
* 0 == link is down, 1 == link is up.
*/
static int
lmc_ds3_get_link_status(lmc_softc_t * const sc)
{
u_int16_t link_status;
lmc_mii_writereg(sc, 0, 17, 7);
link_status = lmc_mii_readreg(sc, 0, 18);
if ((link_status & LMC_FRAMER_REG0_DLOS) == 0)
return 1;
else
return 0;
}
/*
* 0 == 16bit, 1 == 32bit
*/
static void
lmc_ds3_set_crc_length(lmc_softc_t * const sc, int state)
{
if (state == LMC_CTL_CRC_LENGTH_32) {
/* 32 bit */
sc->lmc_miireg16 |= LMC_MII16_DS3_CRC;
sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
} else {
/* 16 bit */
sc->lmc_miireg16 &= ~LMC_MII16_DS3_CRC;
sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
}
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
static void
lmc_ssi_set_link_status(lmc_softc_t * const sc, int state)
{
if (state == LMC_LINK_UP) {
sc->lmc_miireg16 |= (LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS);
printf(LMC_PRINTF_FMT ": asserting DTR and RTS\n",
LMC_PRINTF_ARGS);
} else {
sc->lmc_miireg16 &= ~(LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS);
printf(LMC_PRINTF_FMT ": deasserting DTR and RTS\n",
LMC_PRINTF_ARGS);
}
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
/*
* 0 == 16bit, 1 == 32bit
*/
static void
lmc_ssi_set_crc_length(lmc_softc_t * const sc, int state)
{
if (state == LMC_CTL_CRC_LENGTH_32) {
/* 32 bit */
sc->lmc_miireg16 |= LMC_MII16_SSI_CRC;
sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4;
} else {
/* 16 bit */
sc->lmc_miireg16 &= ~LMC_MII16_SSI_CRC;
sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2;
}
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}
int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
lmc_softc_t *sc = dev_to_sc(dev);
lmc_ctl_t ctl;
int ret = -EOPNOTSUPP;
u16 regVal;
unsigned long flags;
lmc_trace(dev, "lmc_ioctl in");
switch (cmd) {
case LMCIOCGINFO:
if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
ret = -EFAULT;
else
ret = 0;
break;
case LMCIOCSINFO:
if (!capable(CAP_NET_ADMIN)) {
ret = -EPERM;
break;
}
if(dev->flags & IFF_UP){
ret = -EBUSY;
break;
}
if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
ret = -EFAULT;
break;
}
spin_lock_irqsave(&sc->lmc_lock, flags);
sc->lmc_media->set_status (sc, &ctl);
if(ctl.crc_length != sc->ictl.crc_length) {
sc->lmc_media->set_crc_length(sc, ctl.crc_length);
if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
else
sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
}
spin_unlock_irqrestore(&sc->lmc_lock, flags);
ret = 0;
break;
case LMCIOCIFTYPE:
{
u16 old_type = sc->if_type;
u16 new_type;
if (!capable(CAP_NET_ADMIN)) {
ret = -EPERM;
break;
}
if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
ret = -EFAULT;
break;
}
if (new_type == old_type)
{
ret = 0 ;
break;
}
spin_lock_irqsave(&sc->lmc_lock, flags);
lmc_proto_close(sc);
sc->if_type = new_type;
lmc_proto_attach(sc);
ret = lmc_proto_open(sc);
spin_unlock_irqrestore(&sc->lmc_lock, flags);
break;
}
case LMCIOCGETXINFO:
spin_lock_irqsave(&sc->lmc_lock, flags);
sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
sc->lmc_xinfo.PciSlotNumber = 0;
sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
sc->lmc_xinfo.XilinxRevisionNumber =
lmc_mii_readreg (sc, 0, 3) & 0xf;
sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
spin_unlock_irqrestore(&sc->lmc_lock, flags);
sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
sizeof(struct lmc_xinfo)))
ret = -EFAULT;
else
ret = 0;
break;
case LMCIOCGETLMCSTATS:
spin_lock_irqsave(&sc->lmc_lock, flags);
if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
sc->extra_stats.framingBitErrorCount +=
lmc_mii_readreg(sc, 0, 18) & 0xff;
lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
sc->extra_stats.framingBitErrorCount +=
(lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
sc->extra_stats.lineCodeViolationCount +=
lmc_mii_readreg(sc, 0, 18) & 0xff;
lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
sc->extra_stats.lineCodeViolationCount +=
(lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
sc->extra_stats.lossOfFrameCount +=
(regVal & T1FRAMER_LOF_MASK) >> 4;
sc->extra_stats.changeOfFrameAlignmentCount +=
(regVal & T1FRAMER_COFA_MASK) >> 2;
sc->extra_stats.severelyErroredFrameCount +=
regVal & T1FRAMER_SEF_MASK;
}
spin_unlock_irqrestore(&sc->lmc_lock, flags);
if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
sizeof(sc->lmc_device->stats)) ||
copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
&sc->extra_stats, sizeof(sc->extra_stats)))
ret = -EFAULT;
else
ret = 0;
break;
case LMCIOCCLEARLMCSTATS:
if (!capable(CAP_NET_ADMIN)) {
ret = -EPERM;
break;
}
spin_lock_irqsave(&sc->lmc_lock, flags);
memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
sc->extra_stats.check = STATCHECK;
sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
spin_unlock_irqrestore(&sc->lmc_lock, flags);
ret = 0;
break;
case LMCIOCSETCIRCUIT:
if (!capable(CAP_NET_ADMIN)){
ret = -EPERM;
break;
}
if(dev->flags & IFF_UP){
ret = -EBUSY;
break;
}
if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
ret = -EFAULT;
break;
}
spin_lock_irqsave(&sc->lmc_lock, flags);
sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
sc->ictl.circuit_type = ctl.circuit_type;
spin_unlock_irqrestore(&sc->lmc_lock, flags);
ret = 0;
break;
case LMCIOCRESET:
if (!capable(CAP_NET_ADMIN)){
ret = -EPERM;
break;
}
spin_lock_irqsave(&sc->lmc_lock, flags);
printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
lmc_running_reset (dev);
printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
spin_unlock_irqrestore(&sc->lmc_lock, flags);
ret = 0;
break;
#ifdef DEBUG
case LMCIOCDUMPEVENTLOG:
if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
ret = -EFAULT;
break;
}
if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
sizeof(lmcEventLogBuf)))
ret = -EFAULT;
else
ret = 0;
break;
#endif
case LMCIOCT1CONTROL:
if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
ret = -EOPNOTSUPP;
break;
}
break;
case LMCIOCXILINX:
{
struct lmc_xilinx_control xc;
if (!capable(CAP_NET_ADMIN)){
ret = -EPERM;
break;
}
netif_stop_queue(dev);
if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
ret = -EFAULT;
break;
}
switch(xc.command){
case lmc_xilinx_reset:
{
u16 mii;
spin_lock_irqsave(&sc->lmc_lock, flags);
mii = lmc_mii_readreg (sc, 0, 16);
lmc_gpio_mkinput(sc, 0xff);
lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
sc->lmc_gpio &= ~LMC_GEP_RESET;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
udelay(50);
sc->lmc_gpio |= LMC_GEP_RESET;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
lmc_gpio_mkinput(sc, 0xff);
sc->lmc_media->set_link_status (sc, 1);
sc->lmc_media->set_status (sc, NULL);
{
int i;
for(i = 0; i < 5; i++){
lmc_led_on(sc, LMC_DS3_LED0);
mdelay(100);
lmc_led_off(sc, LMC_DS3_LED0);
lmc_led_on(sc, LMC_DS3_LED1);
mdelay(100);
lmc_led_off(sc, LMC_DS3_LED1);
lmc_led_on(sc, LMC_DS3_LED3);
mdelay(100);
lmc_led_off(sc, LMC_DS3_LED3);
lmc_led_on(sc, LMC_DS3_LED2);
mdelay(100);
lmc_led_off(sc, LMC_DS3_LED2);
}
}
spin_unlock_irqrestore(&sc->lmc_lock, flags);
ret = 0x0;
}
break;
case lmc_xilinx_load_prom:
{
u16 mii;
int timeout = 500000;
spin_lock_irqsave(&sc->lmc_lock, flags);
mii = lmc_mii_readreg (sc, 0, 16);
lmc_gpio_mkinput(sc, 0xff);
lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
udelay(50);
sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
(timeout-- > 0))
cpu_relax();
lmc_gpio_mkinput(sc, 0xff);
spin_unlock_irqrestore(&sc->lmc_lock, flags);
ret = 0x0;
break;
}
case lmc_xilinx_load:
{
char *data;
int pos;
int timeout = 500000;
if (!xc.data) {
ret = -EINVAL;
break;
}
data = kmalloc(xc.len, GFP_KERNEL);
if (!data) {
ret = -ENOMEM;
break;
}
if(copy_from_user(data, xc.data, xc.len))
{
kfree(data);
ret = -ENOMEM;
break;
}
printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
spin_lock_irqsave(&sc->lmc_lock, flags);
lmc_gpio_mkinput(sc, 0xff);
sc->lmc_gpio = 0x00;
sc->lmc_gpio &= ~LMC_GEP_DP;
sc->lmc_gpio &= ~LMC_GEP_RESET;
sc->lmc_gpio |= LMC_GEP_MODE;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
udelay(50);
lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
sc->lmc_gpio = 0x00;
sc->lmc_gpio |= LMC_GEP_MODE;
sc->lmc_gpio |= LMC_GEP_DATA;
sc->lmc_gpio |= LMC_GEP_CLK;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
(timeout-- > 0))
cpu_relax();
printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
for(pos = 0; pos < xc.len; pos++){
switch(data[pos]){
case 0:
sc->lmc_gpio &= ~LMC_GEP_DATA;
break;
case 1:
sc->lmc_gpio |= LMC_GEP_DATA;
break;
default:
printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
sc->lmc_gpio |= LMC_GEP_DATA;
}
sc->lmc_gpio &= ~LMC_GEP_CLK;
sc->lmc_gpio |= LMC_GEP_MODE;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
udelay(1);
sc->lmc_gpio |= LMC_GEP_CLK;
sc->lmc_gpio |= LMC_GEP_MODE;
LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
udelay(1);
}
if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
}
else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
}
else {
printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
}
lmc_gpio_mkinput(sc, 0xff);
sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
spin_unlock_irqrestore(&sc->lmc_lock, flags);
kfree(data);
ret = 0;
break;
}
default:
ret = -EBADE;
break;
}
netif_wake_queue(dev);
sc->lmc_txfull = 0;
}
break;
default:
ret = lmc_proto_ioctl (sc, ifr, cmd);
break;
}
static int
lmc_t1_get_link_status(lmc_softc_t * const sc){
u_int16_t link_status;
lmc_mii_writereg(sc, 0, 17, T1FRAMER_ALARM1_STATUS );
link_status = lmc_mii_readreg(sc, 0, 18);
/*
* LMC 1200 LED definitions
* led0 yellow = far-end adapter is in Red alarm condition
* led1 blue = received an Alarm Indication signal (upstream failure)
* led2 Green = power to adapter, Gate Array loaded & driver attached
* led3 red = Loss of Signal (LOS) or out of frame (OOF) conditions
* detected on T3 receive signal
*/
/* detect a change in Blue alarm indication signal */
if( (sc->t1_alarm1_status & T1F_RAIS) != (link_status & T1F_RAIS) )
{
if( link_status & T1F_RAIS )
{ /* turn on blue LED */
printf("%s: link status: RAIS turn ON Blue %x\n", sc->lmc_xname, link_status); /* DEBUG */
lmc_led_on(sc, LMC_DS3_LED1);
}
else
{ /* turn off blue LED */
printf("%s: link status: RAIS turn OFF Blue %x\n", sc->lmc_xname, link_status ); /* DEBUG */
lmc_led_off(sc, LMC_DS3_LED1);
}
}
/*
* T1F_RYEL wiggles quite a bit,
* taking it out until I understand why -baz 6/22/99
*/
/* Yellow alarm indication */
if( (sc->t1_alarm1_status & T1F_RMYEL) !=
(link_status & T1F_RMYEL) )
{
if( (link_status & (T1F_RYEL | T1F_RMYEL)) == 0 )
{
/* turn off yellow LED */
printf("%s: link status: RYEL turn OFF Yellow %x\n", sc->lmc_xname, link_status); /* DEBUG */
lmc_led_off(sc, LMC_DS3_LED0);
}
else
{
/* turn on yellow LED */
printf("%s: link status: RYEL turn ON Yellow %x\n", sc->lmc_xname, link_status); /* DEBUG */
lmc_led_on(sc, LMC_DS3_LED0);
}
}
sc->t1_alarm1_status = link_status;
lmc_mii_writereg(sc, 0, 17, T1FRAMER_ALARM2_STATUS );
sc->t1_alarm2_status = lmc_mii_readreg(sc, 0, 18);
/* link status based upon T1 receive loss of frame or
* loss of signal - RED alarm indication */
if ((link_status & (T1F_RLOF | T1F_RLOS)) == 0)
return 1;
else
return 0;
}
static void
lmc_t1_init(lmc_softc_t * const sc)
{
u_int16_t mii16;
int i;
sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1200;
mii16 = lmc_mii_readreg(sc, 0, 16);
mii16 &= ~LMC_MII16_T1_XOE;
lmc_mii_writereg (sc, 0, 16, mii16);
sc->lmc_miireg16 = mii16;
/* reset 8370 */
mii16 &= ~LMC_MII16_T1_RST;
lmc_mii_writereg(sc, 0, 16, mii16 | LMC_MII16_T1_RST);
lmc_mii_writereg(sc, 0, 16, mii16);
/* set T1 or E1 line impedance */
/* mii16 &= ~LMC_MII16_T1_Z; */
mii16 |= LMC_MII16_T1_Z;
lmc_mii_writereg(sc, 0, 16, mii16);
/* Standard LMC1200 init code */
lmc_t1_write(sc, 0x01, 0x1B); /* CR0 - primary control */
lmc_t1_write(sc, 0x02, 0x42); /* JAT_CR - jitter atten config */
lmc_t1_write(sc, 0x14, 0x00); /* LOOP - loopback config */
lmc_t1_write(sc, 0x15, 0x00); /* DL3_TS - xtrnl datalink timeslot */
lmc_t1_write(sc, 0x18, 0xFF); /* PIO - programmable I/O */
lmc_t1_write(sc, 0x19, 0x30); /* POE - programmable OE */
lmc_t1_write(sc, 0x1A, 0x0F); /* CMUX - clock input mux */
lmc_t1_write(sc, 0x20, 0x41); /* LIU_CR - RX LIU config */
lmc_t1_write(sc, 0x22, 0x76); /* RLIU_CR - RX LIU config */
lmc_t1_write(sc, 0x40, 0x03); /* RCR0 - RX config */
lmc_t1_write(sc, 0x45, 0x00); /* RALM - RX alarm config */
lmc_t1_write(sc, 0x46, 0x05); /* LATCH - RX alarm/err/cntr latch */
lmc_t1_write(sc, 0x68, 0x40); /* TLIU_CR - TX LIU config */
lmc_t1_write(sc, 0x70, 0x0D); /* TCR0 - TX framer config */
lmc_t1_write(sc, 0x71, 0x05); /* TCR1 - TX config */
lmc_t1_write(sc, 0x72, 0x0B); /* TFRM - TX frame format */
lmc_t1_write(sc, 0x73, 0x00); /* TERROR - TX error insert */
lmc_t1_write(sc, 0x74, 0x00); /* TMAN - TX manual Sa/FEBE config */
lmc_t1_write(sc, 0x75, 0x00); /* TALM - TX alarm signal config */
lmc_t1_write(sc, 0x76, 0x00); /* TPATT - TX test pattern config */
lmc_t1_write(sc, 0x77, 0x00); /* TLB - TX inband loopback confg */
lmc_t1_write(sc, 0x90, 0x05); /* CLAD_CR - clock rate adapter confg */
lmc_t1_write(sc, 0x91, 0x05); /* CSEL - clad freq sel */
lmc_t1_write(sc, 0xA6, 0x00); /* DL1_CTL - DL1 control */
lmc_t1_write(sc, 0xB1, 0x00); /* DL2_CTL - DL2 control */
lmc_t1_write(sc, 0xD0, 0x47); /* SBI_CR - sys bus iface config */
lmc_t1_write(sc, 0xD1, 0x70); /* RSB_CR - RX sys bus config */
lmc_t1_write(sc, 0xD4, 0x30); /* TSB_CR - TX sys bus config */
for (i=0; i<32; i++)
{
lmc_t1_write(sc, 0x0E0+i, 0x00); /*SBCn sysbus perchannel ctl */
lmc_t1_write(sc, 0x100+i, 0x00); /* TPCn - TX per-channel ctl */
lmc_t1_write(sc, 0x180+i, 0x00); /* RPCn - RX per-channel ctl */
}
for (i=1; i<25; i++)
{ lmc_t1_write(sc, 0x0E0+i, 0x0D);
/* SBCn - sys bus per-channel ctl */
}
mii16 |= LMC_MII16_T1_XOE;
lmc_mii_writereg(sc, 0, 16, mii16);
sc->lmc_miireg16 = mii16;
}
static int lmc_t1_read(lmc_softc_t * const sc, int a)
{
lmc_mii_writereg(sc, 0, 17, a);
return lmc_mii_readreg(sc, 0, 18);
}
/*
* The framer regs are multiplexed through MII regs 17 & 18
* write the register address to MII reg 17 and the * data to MII reg 18. */
static void lmc_t1_write(lmc_softc_t * const sc, int a, int d)
{
lmc_mii_writereg(sc, 0, 17, a);
lmc_mii_writereg(sc, 0, 18, d);
}
void
lmc_led_off(lmc_softc_t * const sc, u_int32_t led)
{
sc->lmc_miireg16 |= led;
lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
}