Ejemplo n.º 1
0
/*
 * Remove NAND device.
 */
static int __devexit lpc32xx_nand_remove(struct platform_device *pdev)
{
	u32 tmp;
	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
	struct mtd_info *mtd = &host->mtd;

	nand_release(mtd);

	/* Free the DMA channel used by us */
	lpc32xx_dma_ch_disable(host->dmach);
	lpc32xx_dma_dealloc_llist(host->dmach);
	lpc32xx_dma_ch_put(host->dmach);
	host->dmach = -1;

	dma_free_coherent(&pdev->dev, host->dma_buf_len,
		host->data_buf, host->data_buf_dma);

	/* Force CE high */
	tmp = __raw_readl(SLC_CTRL(host->io_base));
	tmp &= ~SLCCFG_CE_LOW;
	__raw_writel(tmp, SLC_CTRL(host->io_base));

	lpc32xx_wp_enable(host);
	clk_disable(host->clk);
	clk_put(host->clk);

	iounmap(host->io_base);

	kfree(host);

	return 0;
}
Ejemplo n.º 2
0
static int lpc3xxx_pcm_hw_free(struct snd_pcm_substream *substream)
{
	struct lpc3xxx_dma_data *prtd = substream->runtime->private_data;

	/* Return the DMA channel */
	if (prtd->dmach != -1) {
		lpc32xx_dma_ch_disable(prtd->dmach);
		lpc32xx_dma_dealloc_llist(prtd->dmach);
		lpc32xx_dma_ch_put(prtd->dmach);
		prtd->dmach = -1;
	}

	return 0;
}
Ejemplo n.º 3
0
static int lpc3xxx_pcm_suspend(struct snd_soc_dai *dai)
{
	struct snd_pcm_runtime *runtime = dai->runtime;
	struct lpc3xxx_dma_data *prtd;

	if (runtime == NULL)
		return 0;

	prtd = runtime->private_data;

	/* Disable the DMA channel */
	lpc32xx_dma_ch_disable(prtd->dmach);

	return 0;
}
Ejemplo n.º 4
0
int lpc32xx_dma_ch_put(int ch)
{
	u32 tmp;

	if (!VALID_CHANNEL(ch))
		return -EINVAL;

	/* If the channel is already disabled, return */
	if (dma_ctrl.dma_channels[ch].name == NULL)
		return -EINVAL;

	tmp = __raw_readl(DMACH_CONFIG_CH(DMAIOBASE, ch));
	tmp &= ~DMAC_CHAN_ENABLE;
	__raw_writel(tmp, DMACH_CONFIG_CH(DMAIOBASE, ch));

	__dma_regs_lock();
	lpc32xx_dma_ch_disable(ch);
	dma_clocks_down();
	__dma_regs_unlock();

	dma_ctrl.dma_channels[ch].name = NULL;

	return 0;
}
Ejemplo n.º 5
0
/*
 * Probe for NAND controller
 */
static int __init lpc32xx_nand_probe(struct platform_device *pdev)
{
	struct lpc32xx_nand_host *host;
	struct mtd_info *mtd;
	struct nand_chip *chip;
	struct resource *rc;
	int res;

	rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (rc == NULL) {
		dev_err(&pdev->dev,"No memory resource found for"
			" device\n");
		return -ENXIO;
	}

	/* Allocate memory for the device structure (and zero it) */
	host = kzalloc(sizeof(struct lpc32xx_nand_host), GFP_KERNEL);
	if (!host) {
		dev_err(&pdev->dev,"failed to allocate device structure\n");
		return -ENOMEM;
	}
	host->io_base_dma = (dma_addr_t) rc->start;

	host->io_base = ioremap(rc->start, rc->end - rc->start + 1);
	if (host->io_base == NULL) {
		dev_err(&pdev->dev,"ioremap failed\n");
		res = -EIO;
		goto err_exit1;
	}

	host->ncfg = pdev->dev.platform_data;
	if (!host->ncfg) {
		dev_err(&pdev->dev,"Missing platform data\n");
		res = -ENOENT;
		goto err_exit1;
	}

	mtd = &host->mtd;
	chip = &host->nand_chip;
	chip->priv = host;
	mtd->priv = chip;
	mtd->owner = THIS_MODULE;
	mtd->dev.parent = &pdev->dev;

	/* Get NAND clock */
	host->clk = clk_get(&pdev->dev, "nand_ck");
	if (IS_ERR(host->clk)) {
		 dev_err(&pdev->dev,"Clock failure\n");
		res = -ENOENT;
		goto err_exit2;
	}
	clk_enable(host->clk);

	/* Set NAND IO addresses and command/ready functions */
	chip->IO_ADDR_R = SLC_DATA(host->io_base);
	chip->IO_ADDR_W = SLC_DATA(host->io_base);
	chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
	chip->dev_ready = lpc32xx_nand_device_ready;
	chip->chip_delay = 20; /* 20us command delay time */

	/* Init NAND controller */
	lpc32xx_nand_setup(host);
	lpc32xx_wp_disable(host);

	platform_set_drvdata(pdev, host);

	/* NAND callbacks for LPC32xx SLC hardware */
	chip->ecc.mode = NAND_ECC_HW_SYNDROME;
	chip->read_byte = lpc32xx_nand_read_byte;
	chip->read_buf = lpc32xx_nand_read_buf;
	chip->write_buf = lpc32xx_nand_write_buf;
	chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
	chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
	chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
	chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
	chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
	chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
	chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
	chip->ecc.correct   = nand_correct_data;
	chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
	chip->verify_buf = lpc32xx_verify_buf;

	/*
	 * Allocate a large enough buffer for a single huge page plus
	 * extra space for the spare area and ECC storage area
	 */
	host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
	host->data_buf = dma_alloc_coherent(&pdev->dev, host->dma_buf_len,
		&host->data_buf_dma, GFP_KERNEL);
	if (host->data_buf == NULL) {
		dev_err(&pdev->dev, "Error allocating memory\n");
		res = -ENOMEM;
		goto err_exit3;
	}

	/* Get free DMA channel and alloc DMA descriptor link list */
	res = lpc32xx_nand_dma_setup(host, LPC32XX_MAX_DMA_DESCRIPTORS);
	if(res) {
		res = -EIO;
		goto err_exit4;
	}

	init_waitqueue_head(&host->dma_waitq);

	/* Find NAND device */
	if (nand_scan_ident(mtd, 1)) {
		res = -ENXIO;
		goto err_exit5;
	}

	/* OOB and ECC CPU and DMA work areas */
	host->ecc_buf_dma = host->data_buf_dma + LPC32XX_DMA_DATA_SIZE;
	host->ecc_buf = (uint32_t *) (host->data_buf + LPC32XX_DMA_DATA_SIZE);

	/*
	 * Small page FLASH has a unique OOB layout, but large and huge
	 * page FLASH use the standard layout. Small page FLASH uses a
	 * custom BBT marker layout.
	 */
	if (mtd->writesize <= 512)
		chip->ecc.layout = &lpc32xx_nand_oob_16;

	/* These sizes remain the same regardless of page size */
	chip->ecc.size = 256;
	chip->ecc.bytes = LPC32XX_SLC_DEV_ECC_BYTES;
	chip->ecc.prepad = chip->ecc.postpad = 0;

	/* Avoid extra scan if using BBT, setup BBT support */
	if (host->ncfg->use_bbt) {
		chip->options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;

		/*
		 * Use a custom BBT marker setup for small page FLASH that
		 * won't interfere with the ECC layout. Large and huge page
		 * FLASH use the standard layout.
		 */
		if (mtd->writesize <= 512) {
			chip->bbt_td = &bbt_smallpage_main_descr;
			chip->bbt_md = &bbt_smallpage_mirror_descr;
		}
	}

	/*
	 * Fills out all the uninitialized function pointers with the defaults
	 */
	if (nand_scan_tail(mtd)) {
		res = -ENXIO;
		goto err_exit5;
	}

	/* Standard layout in FLASH for bad block tables */
	if (host->ncfg->use_bbt) {
		if (nand_default_bbt(mtd) < 0)
			dev_err(&pdev->dev, "Error initializing default bad"
				" block tables\n");
	}

	res = lpc32xx_add_partitions(host);
	if (!res)
		return res;

	nand_release(mtd);

err_exit5:
	/* Free the DMA channel used by us */
	lpc32xx_dma_ch_disable(host->dmach);
	lpc32xx_dma_dealloc_llist(host->dmach);
	lpc32xx_dma_ch_put(host->dmach);
	host->dmach = -1;
err_exit4:
	dma_free_coherent(&pdev->dev, host->dma_buf_len,
		host->data_buf, host->data_buf_dma);
err_exit3:
	clk_disable(host->clk);
	clk_put(host->clk);
	platform_set_drvdata(pdev, NULL);
err_exit2:
	lpc32xx_wp_enable(host);
	iounmap(host->io_base);
err_exit1:
	kfree(host);

	return res;
}
Ejemplo n.º 6
0
static int lpc3xxx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
	struct snd_pcm_runtime *rtd = substream->runtime;
	struct lpc3xxx_dma_data *prtd = rtd->private_data;
	int i, ret = 0;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
		prtd->period_ptr = prtd->dma_cur = prtd->dma_buffer;
		lpc32xx_dma_flush_llist(prtd->dmach);

		/* Queue a few buffers to start DMA */
		for (i = 0; i < NUMLINKS; i++) {
			if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
				lpc32xx_dma_queue_llist_entry(prtd->dmach, (void *) prtd->period_ptr,
#if defined(CONFIG_SND_LPC32XX_USEI2S1)
					(void *) I2S_TX_FIFO(LPC32XX_I2S1_BASE),
#else
					(void *) I2S_TX_FIFO(LPC32XX_I2S0_BASE),
#endif
					prtd->period_size);
			}
			else {
				lpc32xx_dma_queue_llist_entry(prtd->dmach,
#if defined(CONFIG_SND_LPC32XX_USEI2S1)
				(void *) I2S_RX_FIFO(LPC32XX_I2S1_BASE),
#else
				(void *) I2S_RX_FIFO(LPC32XX_I2S0_BASE),
#endif
				(void *) prtd->period_ptr, prtd->period_size);

			}

			prtd->period_ptr += prtd->period_size;
		}
		break;

	case SNDRV_PCM_TRIGGER_STOP:
		lpc32xx_dma_flush_llist(prtd->dmach);
		lpc32xx_dma_ch_disable(prtd->dmach);
		break;

	case SNDRV_PCM_TRIGGER_SUSPEND:
		break;

	case SNDRV_PCM_TRIGGER_RESUME:
		break;

	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		lpc32xx_dma_ch_pause_unpause(prtd->dmach, 1);
		break;

	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		lpc32xx_dma_ch_pause_unpause(prtd->dmach, 0);
		break;

	default:
		ret = -EINVAL;
	}

	return ret;
}