int disphal_deinit_overlay_to_memory(void)
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = DISP_WDMA; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 0;
portStruct.Security = 0;
portStruct.domain = 0; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
disp_module_clock_off(DISP_MODULE_WDMA0, "disphal overlay2mem");
return 0;
}
unsigned int _m4u_g2d_init(void)
{
M4U_PORT_STRUCT m4u_port;
m4u_port.ePortID = M4U_PORT_G2D_R;
m4u_port.Virtuality = 1;
m4u_port.Security = 0;
m4u_port.Distance = 1;
m4u_port.Direction = 0;
m4u_config_port(&m4u_port);
m4u_port.ePortID = M4U_PORT_G2D_W;
m4u_port.Virtuality = 1;
m4u_port.Security = 0;
m4u_port.Distance = 1;
m4u_port.Direction = 0;
m4u_config_port(&m4u_port);
return 0;
}
/*****************************************************************************
* FUNCTION
* _mjc_WaitEvent
* DESCRIPTION
*
* PARAMETERS
* None.
* RETURNS
* None.
****************************************************************************/
static void _mjc_m4uConfigPort(void)
{
int u4Status;
M4U_PORT_STRUCT rM4uPort;
rM4uPort.Virtuality = 1;
rM4uPort.Security = 0;
rM4uPort.Distance = 0;
rM4uPort.Direction = 0;
rM4uPort.domain = 3;
rM4uPort.ePortID = M4U_PORT_MJC_MV_RD;
u4Status = m4u_config_port(&rM4uPort);
if (u4Status != 0)
{
MJCMSG("[ERROR] m4u_config_port(%d) fail!! status = %d\n", rM4uPort.ePortID, u4Status);
}
rM4uPort.ePortID = M4U_PORT_MJC_MV_WR;
u4Status = m4u_config_port(&rM4uPort);
if (u4Status != 0)
{
MJCMSG("[ERROR] m4u_config_port(%d) fail!! status = %d\n", rM4uPort.ePortID, u4Status);
}
rM4uPort.ePortID = M4U_PORT_MJC_DMA_RD;
u4Status = m4u_config_port(&rM4uPort);
if (u4Status != 0)
{
MJCMSG("[ERROR] m4u_config_port(%d) fail!! status = %d\n", rM4uPort.ePortID, u4Status);
}
rM4uPort.ePortID = M4U_PORT_MJC_DMA_WR;
u4Status = m4u_config_port(&rM4uPort);
if (u4Status != 0)
{
MJCMSG("[ERROR] m4u_config_port(%d) fail!! status = %d\n", rM4uPort.ePortID, u4Status);
}
}
static int _build_path_rdma_dpi(void)
{
int ret = 0;
DISP_MODULE_ENUM dst_module = 0;
pgc->mode = EXTD_RDMA_DPI_MODE;
pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_RDMA1_DISP, pgc->cmdq_handle_config);
if(pgc->dpmgr_handle)
{
EXT_DISP_LOG("dpmgr create path SUCCESS(%p)\n", pgc->dpmgr_handle);
}
else
{
EXT_DISP_LOG("dpmgr create path FAIL\n");
return -1;
}
dst_module = _get_dst_module_by_lcm(pgc->plcm);
dpmgr_path_set_dst_module(pgc->dpmgr_handle, dst_module);
EXT_DISP_LOG("dpmgr set dst module FINISHED(%s)\n", ddp_get_module_name(dst_module));
{
M4U_PORT_STRUCT sPort;
sPort.ePortID = M4U_PORT_DISP_RDMA1;
sPort.Virtuality = ext_disp_use_m4u;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
ret = m4u_config_port(&sPort);
if(ret == 0)
{
EXT_DISP_LOG("config M4U Port %s to %s SUCCESS\n",ddp_get_module_name(DISP_MODULE_RDMA1), ext_disp_use_m4u?"virtual":"physical");
}
else
{
EXT_DISP_LOG("config M4U Port %s to %s FAIL(ret=%d)\n",ddp_get_module_name(DISP_MODULE_RDMA1), ext_disp_use_m4u?"virtual":"physical", ret);
return -1;
}
}
dpmgr_set_lcm_utils(pgc->dpmgr_handle, pgc->plcm->drv);
dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_IF_VSYNC);
dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_DONE);
return ret;
}
int hdmi_allocate_hdmi_buffer(void)
{
M4U_PORT_STRUCT m4uport;
int hdmiPixelSize = p->hdmi_width * p->hdmi_height;
int hdmiDataSize = hdmiPixelSize * hdmi_bpp;
int hdmiBufferSize = hdmiDataSize * 4;
HDMI_FUNC();
hdmi_va = (unsigned int) vmalloc(hdmiBufferSize);
if (((void *) hdmi_va) == NULL)
{
HDMI_LOG("vmalloc %dbytes fail!!!\n", hdmiBufferSize);
return -1;
}
memset((void *) hdmi_va, 0x80, hdmiBufferSize);
//RDMA1
if (m4u_alloc_mva(M4U_CLNTMOD_RDMA, hdmi_va, hdmiBufferSize, 0, 0, &hdmi_mva_r))
{
HDMI_LOG("m4u_alloc_mva for hdmi_mva_r fail\n");
return -1;
}
memset((void *) &m4uport, 0, sizeof(M4U_PORT_STRUCT));
m4uport.ePortID = M4U_PORT_RDMA1;
m4uport.Virtuality = 1;
m4uport.domain = 0;
m4uport.Security = 0;
m4uport.Distance = 1;
m4uport.Direction = 0;
m4u_config_port(&m4uport);
HDMI_LOG("hdmi_va=0x%08x, hdmi_mva_r=0x%08x, hdmi_mva_w=0x%08x\n", hdmi_va, hdmi_mva_r, hdmi_mva_w);
return 0;
}
int m4u_test_main(void)
{
int ret;
M4U_PORT_STRUCT M4uPort;
//allocate memory
gSrcVaBuf = (unsigned int) vmalloc(64 * 64 * 4);
if (!gSrcVaBuf) {
M4UMSG("vmalloc failed.\n");
return -1;
}
gDstVaBuf = (unsigned int) vmalloc(64 * 64 * 4);
if (!gDstVaBuf) {
M4UMSG("vmalloc failed.\n");
return -1;
}
//config port
M4uPort.ePortID = DISP_OVL_0;
M4uPort.Virtuality = 1;
M4uPort.Security = 0;
M4uPort.Distance = 1;
M4uPort.Direction = 0;
m4u_config_port(&M4uPort);
M4uPort.ePortID = DISP_WDMA;
M4uPort.Virtuality = 1;
M4uPort.Security = 0;
M4uPort.Distance = 1;
M4uPort.Direction = 0;
m4u_config_port(&M4uPort);
//allocate mva
ret = m4u_alloc_mva(DISP_OVL_0, gSrcVaBuf, 64 * 64 * 4, 0, 0, &(gSrcMvaBuf));
M4U_ASSERT(0==ret);
m4u_insert_seq_range(DISP_OVL_0, gSrcMvaBuf, gSrcMvaBuf + 64 * 64 * 4 - 1, SEQ_RANGE_LOW_PRIORITY, 1);
M4UMSG("src module=DISP_OVL_0, va=0x%x, mva=0x%x.\n",
gSrcVaBuf, gSrcMvaBuf);
ret = m4u_alloc_mva(DISP_WDMA, gDstVaBuf, 64 * 64 * 4, 0, 0, &(gDstMvaBuf));
M4U_ASSERT(0==ret);
m4u_insert_seq_range(DISP_OVL_0, gDstMvaBuf, gDstMvaBuf + 64 * 64 * 4 - 1, SEQ_RANGE_LOW_PRIORITY, 1);
M4UMSG("dst module=DISP_WDMA, va=0x%x, mva=0x%x.\n",
gDstVaBuf, gDstMvaBuf);
// ddp test
memset((void *)gSrcVaBuf, 0, 64 * 64 * 4);
memcpy((void *)gSrcVaBuf, SRC_BUF_ADDR, 64 * 64 * 4);
memset((void *)gDstVaBuf, 0, 64 * 64 * 4);
m4u_dma_cache_maint(DISP_OVL_0, (void *)gSrcVaBuf, 64 * 64 * 4, M4U_CACHE_FLUSH_BEFORE_HW_READ_MEM);
m4u_dma_cache_maint(DISP_WDMA, (void *)gDstVaBuf, 64 * 64 * 4, M4U_CACHE_FLUSH_BEFORE_HW_READ_MEM);
if ((slt_result = m4u_ddp_test(gSrcMvaBuf, gDstVaBuf, gDstMvaBuf)) == 0)
M4UMSG("case 1 result: success \n");
else {
M4UMSG("case 1 result: fail\n");
M4U_ASSERT(0);
}
//free va & mva
/*m4u_invalid_seq_range(DISP_OVL_0, gSrcMvaBuf, gSrcMvaBuf + 64 * 64 * 4 - 1);
m4u_invalid_seq_range(DISP_WDMA, gDstMvaBuf, gDstMvaBuf + 64 * 64 * 4 - 1);
m4u_dealloc_mva(DISP_OVL_0, gSrcVaBuf, 64 * 64 * 4, gSrcMvaBuf);
m4u_dealloc_mva(DISP_WDMA, gDstVaBuf, 64 * 64 * 4, gDstMvaBuf);*/
vfree((void *)gSrcVaBuf);
vfree((void *)gDstVaBuf);
/*
M4uPort.ePortID = DISP_OVL_0;
M4uPort.Virtuality = 0;
M4uPort.Security = 0;
M4uPort.Distance = 1;
M4uPort.Direction = 0;
m4u_config_port(&M4uPort);
M4uPort.ePortID = DISP_WDMA;
M4uPort.Virtuality = 0;
M4uPort.Security = 0;
M4uPort.Distance = 1;
M4uPort.Direction = 0;
m4u_config_port(&M4uPort);*/
m4u_debug_init();
return 0;
}
/* Will only be used in ioctl(MTK_HDMI_AUDIO_VIDEO_ENABLE) */
static HDMI_STATUS hdmi_drv_init(void)
{
int lcm_width, lcm_height;
int tmpBufferSize;
M4U_PORT_STRUCT portStruct;
HDMI_FUNC();
RETIF(p->output_mode == HDMI_OUTPUT_MODE_DPI_BYPASS, 0);
p->hdmi_width = 1280;
p->hdmi_height = 720;
lcm_width = DISP_GetScreenWidth();
lcm_height = DISP_GetScreenHeight();
//printk("[hdmi]%s, hdmi_width=%d, hdmi_height=%d\n", __func__, p->hdmi_width, p->hdmi_height);
HDMI_LOG("lcm_width=%d, lcm_height=%d\n", lcm_width, lcm_height);
tmpBufferSize = lcm_width * lcm_height *4 * 4;
temp_va = (unsigned int) vmalloc(tmpBufferSize);
if (((void*) temp_va) == NULL)
{
HDMI_LOG("vmalloc %dbytes fail\n", tmpBufferSize);
return -1;
}
// WDMA1
if (m4u_alloc_mva(M4U_CLNTMOD_WDMA,
temp_va,
tmpBufferSize,
0,
0,
&temp_mva_w))
{
HDMI_LOG("m4u_alloc_mva for temp_mva_w fail\n");
return -1;
}
m4u_dma_cache_maint(M4U_CLNTMOD_WDMA,
temp_va,
tmpBufferSize,
DMA_BIDIRECTIONAL);
portStruct.ePortID = M4U_PORT_WDMA1; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 0; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
HDMI_LOG("temp_va=0x%08x, temp_mva_w=0x%08x\n", temp_va, temp_mva_w);
p->lcm_width = lcm_width;
p->lcm_height = lcm_height;
p->output_video_resolution = hdmi_params->init_config.vformat;
p->output_audio_format = hdmi_params->init_config.aformat;
//#ifdef NEW_HDMI_ARCH
// hdmi_display_path_overlay_config(true);
//#endif
DISP_Config_Overlay_to_Memory(temp_mva_w, 1);
//hdmi_dpi_config_clock(); // configure dpi clock
//hdmi_dpi_power_switch(false); // but dpi power is still off
//hdmi_drv->suspend();
#if 0
LCD_WaitForNotBusy();
LCD_SetOutputMode(3); // LCD write to memory and LCM
#endif
return HDMI_STATUS_OK;
}
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
// DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
if (!disp_drv_dsi_init_context())
return DISP_STATUS_NOT_IMPLEMENTED;
// DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
if(lcm_params->dsi.mode == CMD_MODE) {
#ifndef MT65XX_NEW_DISP
init_lcd();
#endif
init_dsi(isLcmInited);
mdelay(1);
// DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
if (NULL != lcm_drv->init && !isLcmInited)
{
lcm_drv->init();
DSI_LP_Reset();
}
// DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
#ifndef MT65XX_NEW_DISP
DSI_clk_HS_mode(0);
#else
DSI_clk_HS_mode(1);
#endif
// DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "%s, line:%d\n", __func__, __LINE__);
DSI_SetMode(lcm_params->dsi.mode);
#ifndef MT65XX_NEW_DISP
init_lcd_te_control();
#endif
}
else {
#ifndef MT65XX_NEW_DISP
init_intermediate_buffers(fbPA);
init_lcd();
init_dpi(isLcmInited);
#endif
if (!isLcmInited)
{
DSI_SetMode(0);
mdelay(100);
DSI_Stop();
}
else
{
is_video_mode_running = true;
}
init_dsi(isLcmInited);
mdelay(1);
if (NULL != lcm_drv->init && !isLcmInited) {
lcm_drv->init();
DSI_LP_Reset();
}
DSI_SetMode(lcm_params->dsi.mode);
#ifndef BUILD_UBOOT
if(lcm_params->dsi.lcm_ext_te_monitor)
{
is_video_mode_running = false;
LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
LCD_TE_Enable(FALSE);
}
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
}
#ifdef MT65XX_NEW_DISP
{
struct disp_path_config_struct config = {0};
config.srcModule = DISP_MODULE_OVL;
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = DISP_GetScreenWidth();
config.bgROI.height = DISP_GetScreenHeight();
config.bgColor = 0x0; // background color
config.pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2;
config.srcROI.x = 0;config.srcROI.y = 0;
config.srcROI.height= DISP_GetScreenHeight();
config.srcROI.width= DISP_GetScreenWidth();
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = OVL_INPUT_FORMAT_RGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.vaddr = fbVA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.src_w = DISP_GetScreenWidth();
config.ovl_config.src_h = DISP_GetScreenHeight();
config.ovl_config.dst_x = 0; // ROI
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = DISP_GetScreenWidth();
config.ovl_config.dst_h = DISP_GetScreenHeight();
config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2; //pixel number
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; // color key
config.ovl_config.aen = 0; // alpha enable
config.ovl_config.alpha = 0;
if(lcm_params->dsi.mode == CMD_MODE)
config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
else
config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER,DISP_GetScreenWidth(),DISP_GetScreenHeight());
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(),32) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
#if defined(MTK_M4U_EXT_PAGE_TABLE)
if(lcm_params->dsi.mode != CMD_MODE)
{
DSI_Wait_VDO_Idle();
disp_path_get_mutex();
}
disp_path_config(&config);
#if 1
// Config FB_Layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_LCD_OVL; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
// hook m4u debug callback function
m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
#endif
if(lcm_params->dsi.mode != CMD_MODE)
{
disp_path_release_mutex();
DSI_Start();
}
#else
if(lcm_params->dsi.mode != CMD_MODE){
#define TIMECNT 1000000
unsigned int reg1 = 0, reg2 = 0, reg3 = 0;
unsigned int timeout_cnt = 0;
unsigned int irq_mask;
// dump before modification
printk("[DISP] pa:0x%x, va:0x%x \n", fbPA, fbVA);
// enable frame done interrupt
disp_path_get_mutex();
OVLEnableIrq(0x2);
disp_path_release_mutex();
while (timeout_cnt < TIMECNT)
{
reg1 = DISP_REG_GET(DISP_REG_OVL_INTSTA);
reg2 = DISP_REG_GET(DISP_REG_OVL_STA);
// frame done interrupt
if (((reg1 & 0x2) == 0x2) && ((reg2 & 0x1) == 0x0))
{
DISP_REG_SET(DISP_REG_OVL_INTSTA, ~reg1);
local_irq_save(irq_mask);
disp_path_get_mutex();
disp_path_config(&config);
disp_path_release_mutex();
#if 1 // defined(MTK_M4U_SUPPORT)
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_LCD_OVL; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
// hook m4u debug callback function
m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
#endif
local_irq_restore(irq_mask);
break;
}
timeout_cnt++;
}
// sw timeout
if (timeout_cnt >= TIMECNT)
{
printk("[DISP] timeout:%d \n", timeout_cnt);
ASSERT(0);
}
// dump after modification
printk("[DISP] cnt:%d \n", timeout_cnt);
}
else
{
disp_path_config(&config);
#if 1 // defined(MTK_M4U_SUPPORT)
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_LCD_OVL; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
// hook m4u debug callback function
m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
#endif
}
#endif
}
#endif
printk("%s, config done\n", __func__);
return DISP_STATUS_OK;
}
int ovl2mem_init(unsigned int session)
{
int ret = -1;
DISPFUNC();
dpmgr_init();
mutex_init(&(pgc->lock));
_ovl2mem_path_lock(__func__);
if(pgc->state > 0)
goto Exit;
#if 0
ret = cmdqCoreRegisterCB(CMDQ_GROUP_DISP, cmdqDdpClockOn,cmdqDdpDumpInfo,cmdqDdpResetEng,cmdqDdpClockOff);
if(ret)
{
DISPERR("cmdqCoreRegisterCB failed, ret=%d \n", ret);
goto done;
}
#endif
ret = cmdqRecCreate(CMDQ_SCENARIO_SUB_DISP,&(pgc->cmdq_handle_config));
if(ret)
{
DISPCHECK("cmdqRecCreate FAIL, ret=%d \n", ret);
goto Exit;
}
else
{
DISPCHECK("cmdqRecCreate SUCCESS, cmdq_handle=%p\n", pgc->cmdq_handle_config);
}
pgc->dpmgr_handle = dpmgr_create_path(DDP_SCENARIO_SUB_OVL_MEMOUT, pgc->cmdq_handle_config);
if(pgc->dpmgr_handle)
{
DISPCHECK("dpmgr create path SUCCESS(%p)\n", pgc->dpmgr_handle);
}
else
{
DISPCHECK("dpmgr create path FAIL\n");
goto Exit;
}
M4U_PORT_STRUCT sPort;
sPort.ePortID = M4U_PORT_DISP_OVL1;
sPort.Virtuality = ovl2mem_use_m4u;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
ret = m4u_config_port(&sPort);
sPort.ePortID = M4U_PORT_DISP_WDMA1;
sPort.Virtuality = ovl2mem_use_m4u;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
ret = m4u_config_port(&sPort);
if(ret == 0)
{
DISPCHECK("config M4U Port %s to %s SUCCESS\n",ddp_get_module_name(DISP_MODULE_OVL1), ovl2mem_use_m4u?"virtual":"physical");
}
else
{
DISPCHECK("config M4U Port %s to %s FAIL(ret=%d)\n",ddp_get_module_name(DISP_MODULE_OVL1), ovl2mem_use_m4u?"virtual":"physical", ret);
goto Exit;
}
dpmgr_path_set_video_mode(pgc->dpmgr_handle, ovl2mem_cmdq_enabled());
dpmgr_path_init(pgc->dpmgr_handle, CMDQ_DISABLE);
dpmgr_path_reset(pgc->dpmgr_handle, CMDQ_DISABLE);
//dpmgr_path_set_dst_module(pgc->dpmgr_handle,DISP_MODULE_ENUM dst_module)
dpmgr_enable_event(pgc->dpmgr_handle, DISP_PATH_EVENT_FRAME_COMPLETE);
pgc->max_layer = 4;
pgc->state = 1;
pgc->session = session;
atomic_set(&g_trigger_ticket, 1);
atomic_set(&g_release_ticket, 1);
Exit:
_ovl2mem_path_unlock(__func__);
DISPMSG("ovl2mem_init done\n");
return ret;
}
int ddp_mem_test2(void)
{
int result = 0;
unsigned int* pSrc;
unsigned int* pDst;
#if 0
DdpkBitbltConfig pddp;
#endif
pSrc= vmalloc(DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
if(pSrc==0)
{
printk("[DDP] error: dma_alloc_coherent error! dma memory not available.\n");
return 0;
}
else
{
printk("[ddp] pSrc=0x%x \n", (unsigned int)pSrc);
}
memcpy((void*)pSrc, data_rgb888_64x64, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
pDst= vmalloc(DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
if(pDst==0)
{
printk("[DDP] error: dma_alloc_coherent error! dma memory not available.\n");
return 0;
}
else
{
printk("[ddp] pDst=0x%x\n", (unsigned int)pDst);
}
memset((void*)pDst, 0, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
/*
disp_power_on(DISP_MODULE_ROT);
disp_power_on(DISP_MODULE_SCL);
disp_power_on(DISP_MODULE_WDMA0);
*/
// config port to virtual
{
M4U_PORT_STRUCT sPort;
sPort.ePortID = M4U_PORT_LCD_W;
sPort.Virtuality = 1;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
m4u_config_port(&sPort);
}
//config
#if 0
pddp.srcX = 0;
pddp.srcY = 0;
pddp.srcW = DDP_TEST_WIDTH;
pddp.srcWStride = DDP_TEST_WIDTH;
pddp.srcH = DDP_TEST_HEIGHT;
pddp.srcHStride = DDP_TEST_HEIGHT;
pddp.srcAddr[0] = (unsigned int)pSrc;
pddp.srcFormat = eRGB888_K;
pddp.srcPlaneNum = 1;
pddp.srcBufferSize[0] = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
pddp.dstX = 0;
pddp.dstY = 0;
pddp.dstW = DDP_TEST_WIDTH;
pddp.dstWStride = DDP_TEST_WIDTH;
pddp.dstH = DDP_TEST_HEIGHT;
pddp.dstHStride = DDP_TEST_HEIGHT;
pddp.dstAddr[0] = (unsigned int)pDst;
pddp.dstFormat = eRGB888_K;
pddp.pitch = DDP_TEST_WIDTH;
pddp.dstPlaneNum = 1;
pddp.dstBufferSize[0] = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
pddp.orientation = 0;
result = DDPK_Bitblt_Config( DDPK_CH_HDMI_0, &pddp );
if(result)
{
printk("[DDP] error: DDPK_Bitblt_Config fail!, ret=%d\n", result);
}
printk("DDP, DDPK_Bitblt module setting: \n");
disp_dump_reg(DISP_MODULE_ROT);
disp_dump_reg(DISP_MODULE_SCL);
disp_dump_reg(DISP_MODULE_WDMA0);
disp_dump_reg(DISP_MODULE_CONFIG);
result = DDPK_Bitblt( DDPK_CH_HDMI_0);
if(result)
{
printk("[DDP] error: DDPK_Bitblt() fail, result=%d \n", result);
}
#endif
// result verify
{
unsigned int diff_cnt = 0;
unsigned int t=0;
unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
for(t=0;t<size;t++)
{
if( *((unsigned char*)pSrc+t) != *((unsigned char*)data_rgb888_64x64+t) )
{
diff_cnt++;
printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
t,
diff_cnt,
*((unsigned char*)pSrc+t),
*((unsigned char*)data_rgb888_64x64+t) );
}
}
if(diff_cnt == 0)
printk("ddp_mem_test src compare result: success \n");
else
{
printk("[DDP] error: ddp_mem_test src compare result: fail \n");
printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
result = -1;
}
}
{
unsigned int diff_cnt = 0;
unsigned int t=0;
unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
for(t=0;t<size;t++)
{
if( *((unsigned char*)pDst+t) != *((unsigned char*)data_rgb888_64x64_golden+t) )
{
diff_cnt++;
printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
t,
diff_cnt,
*((unsigned char*)pDst+t),
*((unsigned char*)data_rgb888_64x64_golden+t) );
}
}
if(diff_cnt == 0)
printk("ddp_mem_test result: success \n");
else
{
printk("[DDP] error: ddp_mem_test result: fail \n");
printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
result = -1;
}
}
/*
disp_power_off(DISP_MODULE_ROT);
disp_power_off(DISP_MODULE_SCL);
disp_power_off(DISP_MODULE_WDMA0);
*/
//dealloc memory
vfree(pSrc);
vfree(pDst);
return result;
}
static DISP_STATUS dsi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
if (!disp_drv_dsi_init_context())
return DISP_STATUS_NOT_IMPLEMENTED;
if(lcm_params->dsi.mode == CMD_MODE) {
#ifndef MT65XX_NEW_DISP
init_lcd();
#endif
init_dsi(isLcmInited);
if (NULL != lcm_drv->init && !isLcmInited)
{
lcm_drv->init();
DSI_LP_Reset();
}
#ifndef MT65XX_NEW_DISP
DSI_clk_HS_mode(0);
#else
DSI_clk_HS_mode(1);
#endif
DSI_SetMode(lcm_params->dsi.mode);
#ifndef MT65XX_NEW_DISP
DPI_PowerOn();
DPI_PowerOff();
init_lcd_te_control();
#endif
}
else {
#ifndef MT65XX_NEW_DISP
init_intermediate_buffers(fbPA);
init_lcd();
init_dpi(isLcmInited);
#endif
if (!isLcmInited)
{
DSI_SetMode(0);
mdelay(100);
DSI_DisableClk();
}
else
{
is_video_mode_running = true;
}
init_dsi(isLcmInited);
if (NULL != lcm_drv->init && !isLcmInited) {
lcm_drv->init();
DSI_LP_Reset();
}
DSI_SetMode(lcm_params->dsi.mode);
#ifndef BUILD_UBOOT
#ifndef MT65XX_NEW_DISP
if(lcm_params->dsi.lcm_ext_te_monitor)
{
is_video_mode_running = false;
LCD_TE_SetMode(LCD_TE_MODE_VSYNC_ONLY);
LCD_TE_SetEdgePolarity(LCM_POLARITY_RISING);
LCD_TE_Enable(FALSE);
}
if(lcm_params->dsi.noncont_clock)
DSI_set_noncont_clk(false, lcm_params->dsi.noncont_clock_period);
if(lcm_params->dsi.lcm_int_te_monitor)
DSI_set_int_TE(false, lcm_params->dsi.lcm_int_te_period);
#endif
#endif
}
#ifdef MT65XX_NEW_DISP
{
struct disp_path_config_struct config = {0};
config.srcModule = DISP_MODULE_OVL;
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = DISP_GetScreenWidth();
config.bgROI.height = DISP_GetScreenHeight();
config.bgColor = 0x0; // background color
config.pitch = DISP_GetScreenWidth()*2;
config.srcROI.x = 0;config.srcROI.y = 0;
config.srcROI.height= DISP_GetScreenHeight();config.srcROI.width= DISP_GetScreenWidth();
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
if(lcm_params->dsi.mode != CMD_MODE)
{
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 0;
disp_path_get_mutex();
disp_path_config_layer(&config.ovl_config);
disp_path_release_mutex();
disp_path_wait_reg_update();
}
// Config FB_Layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_OVL_CH3; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = OVL_INPUT_FORMAT_RGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.dst_x = 0; // ROI
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = DISP_GetScreenWidth();
config.ovl_config.dst_h = DISP_GetScreenHeight();
config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2; //pixel number
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; // color key
config.ovl_config.aen = 0; // alpha enable
config.ovl_config.alpha = 0;
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER,DISP_GetScreenWidth(),DISP_GetScreenHeight());
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(),32) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
if(lcm_params->dsi.mode == CMD_MODE)
config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
else
config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
if(lcm_params->dsi.mode != CMD_MODE)
disp_path_get_mutex();
disp_path_config(&config);
if(lcm_params->dsi.mode != CMD_MODE)
disp_path_release_mutex();
// Disable LK UI layer (Layer2)
if(lcm_params->dsi.mode != CMD_MODE)
{
config.ovl_config.layer = FB_LAYER-1;
config.ovl_config.layer_en = 0;
disp_path_get_mutex();
disp_path_config_layer(&config.ovl_config);
disp_path_release_mutex();
disp_path_wait_reg_update();
}
// Config LK UI layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_OVL_CH2; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
}
#endif
return DISP_STATUS_OK;
}
// ---------------------------------------------------------------------------
// DBI Display Driver Public Functions
// ---------------------------------------------------------------------------
static DISP_STATUS dsi_config_ddp(UINT32 fbPA)
{
struct disp_path_config_struct config = {0};
if (DISP_IsDecoupleMode()) {
config.srcModule = DISP_MODULE_RDMA;
} else {
config.srcModule = DISP_MODULE_OVL;
}
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = lcm_params->width;
config.bgROI.height = lcm_params->height;
config.bgColor = 0x0; // background color
config.pitch = lcm_params->width*2;
config.srcROI.x = 0;config.srcROI.y = 0;
config.srcROI.height= lcm_params->height;
config.srcROI.width= lcm_params->width;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
if(lcm_params->dsi.mode != CMD_MODE)
{
config.ovl_config.layer = DDP_OVL_LAYER_MUN-1;
config.ovl_config.layer_en = 0;
//disp_path_get_mutex();
disp_path_config_layer(&config.ovl_config);
//disp_path_release_mutex();
//disp_path_wait_reg_update();
}
#if 1
// Disable LK UI layer (Layer2)
{
config.ovl_config.layer = DDP_OVL_LAYER_MUN-1-1;
config.ovl_config.layer_en = 0; // disable LK UI layer anyway
//disp_path_get_mutex();
disp_path_config_layer(&config.ovl_config);
//disp_path_release_mutex();
//disp_path_wait_reg_update();
}
#endif
config.ovl_config.layer = DDP_OVL_LAYER_MUN-1;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = eRGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.dst_x = 0; // ROI
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = lcm_params->width;
config.ovl_config.dst_h = lcm_params->height;
config.ovl_config.src_pitch = ALIGN_TO(lcm_params->width, MTK_FB_ALIGNMENT)*2; //pixel number
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; // color key
config.ovl_config.aen = 0; // alpha enable
config.ovl_config.alpha = 0;
/*LCD_LayerSetAddress(DDP_OVL_LAYER_MUN-1, fbPA);
LCD_LayerSetFormat(DDP_OVL_LAYER_MUN-1, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(DDP_OVL_LAYER_MUN-1, 0, 0);
LCD_LayerSetSize(DDP_OVL_LAYER_MUN-1,lcm_params->width,lcm_params->height);
LCD_LayerSetPitch(DDP_OVL_LAYER_MUN-1, ALIGN_TO(lcm_params->width, MTK_FB_ALIGNMENT) * 2);
LCD_LayerEnable(DDP_OVL_LAYER_MUN-1, TRUE); */
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, eRGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER,lcm_params->width,lcm_params->height);
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(lcm_params->width, MTK_FB_ALIGNMENT) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
if(lcm_params->dsi.mode == CMD_MODE)
config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
else
config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
disp_path_config(&config);
if(lcm_params->dsi.mode != CMD_MODE)
{
//DSI_Wait_VDO_Idle();
disp_path_get_mutex();
}
// Config FB_Layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = DISP_OVL_0; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
if(lcm_params->dsi.mode != CMD_MODE)
{
disp_path_release_mutex();
//if(1 == lcm_params->dsi.ufoe_enable)
// UFOE_Start();
//DSI_Start();
}
printk("%s, config done\n", __func__);
return DISP_STATUS_OK;
}
// ---------------------------------------------------------------------------
// DBI Display Driver Public Functions
// ---------------------------------------------------------------------------
static DISP_STATUS dsi_config_ddp(UINT32 fbPA)
{
unsigned long irq_mask;
struct disp_path_config_struct config = {0};
if (DISP_IsDecoupleMode())
{
config.srcModule = DISP_MODULE_RDMA0;
}
else
{
config.srcModule = DISP_MODULE_OVL;
}
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = lcm_params->width;
config.bgROI.height = lcm_params->height;
config.bgColor = 0x0; // background color
config.pitch = lcm_params->width*2;
config.srcROI.x = 0;config.srcROI.y = 0;
config.srcROI.height= lcm_params->height;
config.srcROI.width= lcm_params->width;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.layer = DDP_OVL_LAYER_MUN-1;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = eRGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.dst_x = 0; // ROI
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = lcm_params->width;
config.ovl_config.dst_h = lcm_params->height;
config.ovl_config.src_pitch = ALIGN_TO(lcm_params->width, MTK_FB_ALIGNMENT)*2; //pixel number
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; // color key
config.ovl_config.aen = 0; // alpha enable
config.ovl_config.alpha = 0;
LCD_LayerSetAddress(DDP_OVL_LAYER_MUN-1, fbPA);
LCD_LayerSetFormat(DDP_OVL_LAYER_MUN-1, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(DDP_OVL_LAYER_MUN-1, 0, 0);
LCD_LayerSetSize(DDP_OVL_LAYER_MUN-1,lcm_params->width,lcm_params->height);
LCD_LayerSetPitch(DDP_OVL_LAYER_MUN-1, ALIGN_TO(lcm_params->width, MTK_FB_ALIGNMENT) * 2);
LCD_LayerEnable(DDP_OVL_LAYER_MUN-1, TRUE);
if(lcm_params->dsi.mode == CMD_MODE)
{
config.dstModule = DISP_MODULE_DSI_CMD;// DISP_MODULE_WDMA1
}
else
{
config.dstModule = DISP_MODULE_DSI_VDO;// DISP_MODULE_WDMA1
}
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
if(lcm_params->dsi.mode != CMD_MODE)
{
DSI_Wait_VDO_Idle();
local_irq_save(irq_mask);
disp_path_get_mutex();
}
disp_path_config(&config);
// Config FB_Layer port to be physical.
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_LCD_OVL; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
// hook m4u debug callback function
m4u_set_tf_callback(M4U_CLNTMOD_DISP, &disp_m4u_dump_reg);
if(lcm_params->dsi.mode != CMD_MODE)
{
disp_path_release_mutex();
DSI_Start();
local_irq_restore(irq_mask);
}
printk("%s, config done\n", __func__);
return DISP_STATUS_OK;
}
DPI_STATUS DPI_Capture_Framebuffer(unsigned int pvbuf, unsigned int bpp)
{
unsigned int mva;
unsigned int ret = 0;
M4U_PORT_STRUCT portStruct;
struct disp_path_config_mem_out_struct mem_out = {0};
printk("enter DPI_Capture_FB!\n");
if(bpp == 32)
mem_out.outFormat = eARGB8888;
else if(bpp == 16)
mem_out.outFormat = eRGB565;
else if(bpp == 24)
mem_out.outFormat = eRGB888;
else
printk("DPI_Capture_FB, fb color format not support\n");
printk("before alloc MVA: va = 0x%x, size = %d\n", pvbuf, lcm_params->height*lcm_params->width*bpp/8);
ret = m4u_alloc_mva(DISP_WDMA,
pvbuf,
lcm_params->height*lcm_params->width*bpp/8,
0,
0,
&mva);
if(ret!=0)
{
printk("m4u_alloc_mva() fail! \n");
return DPI_STATUS_OK;
}
printk("addr=0x%x, format=%d \n", mva, mem_out.outFormat);
m4u_dma_cache_maint(DISP_WDMA,
(void *)pvbuf,
lcm_params->height*lcm_params->width*bpp/8,
DMA_BIDIRECTIONAL);
portStruct.ePortID = DISP_WDMA; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 0; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
mem_out.enable = 1;
mem_out.dstAddr = mva;
mem_out.srcROI.x = 0;
mem_out.srcROI.y = 0;
mem_out.srcROI.height= lcm_params->height;
mem_out.srcROI.width= lcm_params->width;
disp_path_get_mutex();
disp_path_config_mem_out(&mem_out);
printk("Wait DPI idle \n");
disp_path_release_mutex();
msleep(20);
disp_path_get_mutex();
mem_out.enable = 0;
disp_path_config_mem_out(&mem_out);
disp_path_release_mutex();
portStruct.ePortID = DISP_WDMA; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 0;
portStruct.Security = 0;
portStruct.domain = 0; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
m4u_dealloc_mva(DISP_WDMA,
pvbuf,
lcm_params->height*lcm_params->width*bpp/8,
mva);
return DPI_STATUS_OK;
}
static DISP_STATUS dpi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
if (!disp_drv_dpi_init_context())
return DISP_STATUS_NOT_IMPLEMENTED;
#ifndef MT65XX_NEW_DISP
init_intermediate_buffers(fbPA);
#else
{
struct disp_path_config_struct config = { 0 };
if (DISP_IsDecoupleMode())
config.srcModule = DISP_MODULE_RDMA;
else
config.srcModule = DISP_MODULE_OVL;
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = DISP_GetScreenWidth();
config.bgROI.height = DISP_GetScreenHeight();
config.bgColor = 0x0; /* background color */
config.srcROI.x = 0;
config.srcROI.y = 0;
config.srcROI.height = DISP_GetScreenHeight();
config.srcROI.width = DISP_GetScreenWidth();
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
#if 0
/* Disable all layers. */
/* First disable FB_Layer. */
disp_path_get_mutex();
config.ovl_config.layer = 0;
config.ovl_config.layer_en = 0;
disp_path_config_layer(&config.ovl_config);
config.ovl_config.layer = 1;
disp_path_config_layer(&config.ovl_config);
config.ovl_config.layer = 2;
disp_path_config_layer(&config.ovl_config);
config.ovl_config.layer = 3;
disp_path_config_layer(&config.ovl_config);
disp_path_release_mutex();
disp_path_wait_reg_update();
#endif
/* Config FB_Layer port to be virtual. */
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = DISP_OVL_0; /* hardware port ID, defined in M4U_PORT_ID_ENUM */
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; /* domain : 0 1 2 3 */
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
/* Reconfig FB_Layer and enable it. */
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = eRGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.dst_x = 0; /* ROI */
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = DISP_GetScreenWidth();
config.ovl_config.dst_h = DISP_GetScreenHeight();
config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(), 32) * 2;
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; /* color key */
config.ovl_config.aen = 0; /* alpha enable */
config.ovl_config.alpha = 0;
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER, DISP_GetScreenWidth(), DISP_GetScreenHeight());
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(), 32) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
config.dstModule = DISP_MODULE_DPI0; /* DISP_MODULE_WDMA1 */
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
disp_path_get_mutex();
disp_path_config(&config);
disp_path_release_mutex();
}
#endif
init_mipi_pll();
init_io_pad();
init_io_driving_current();
init_lcd();
init_dpi(isLcmInited);
if (NULL != lcm_drv->init && !isLcmInited)
lcm_drv->init();
DSI_PowerOn();
DSI_PowerOff();
UFOE_PowerOn();
UFOE_PowerOff();
#ifdef SPM_SODI_ENABLED
spm_sodi_lcm_video_mode(TRUE);
#endif
return DISP_STATUS_OK;
}
static DISP_STATUS dbi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
if (!disp_drv_dbi_init_context())
return DISP_STATUS_NOT_IMPLEMENTED;
#ifdef MT65XX_NEW_DISP
{
struct disp_path_config_struct config = {0};
config.srcModule = DISP_MODULE_OVL;
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = DISP_GetScreenWidth();
config.bgROI.height = DISP_GetScreenHeight();
config.bgColor = 0x0; // background color
config.pitch = DISP_GetScreenWidth()*2;
config.srcROI.x = 0;config.srcROI.y = 0;
config.srcROI.height= DISP_GetScreenHeight();config.srcROI.width= DISP_GetScreenWidth();
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
// Config FB_Layer port to be physical.
#if 1 // defined(MTK_M4U_SUPPORT)
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_LCD_OVL; //hardware port ID, defined in M4U_PORT_ID_ENUM
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; //domain : 0 1 2 3
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
#endif
// Reconfig FB_Layer and enable it.
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = OVL_INPUT_FORMAT_RGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.src_w = DISP_GetScreenWidth();
config.ovl_config.src_h = DISP_GetScreenHeight();
config.ovl_config.dst_x = 0; // ROI
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = DISP_GetScreenWidth();
config.ovl_config.dst_h = DISP_GetScreenHeight();
config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(),32)*2; //pixel number
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; // color key
config.ovl_config.aen = 0; // alpha enable
config.ovl_config.alpha = 0;
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER,DISP_GetScreenWidth(),DISP_GetScreenHeight());
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(),32) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
config.dstModule = DISP_MODULE_DBI;// DISP_MODULE_WDMA1
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
disp_path_config(&config);
disp_bls_config();
}
#endif
init_io_pad();
init_io_driving_current();
init_lcd(isLcmInited);
if (NULL != lcm_drv->init && !isLcmInited) {
lcm_drv->init();
}
init_lcd_te_control();
return DISP_STATUS_OK;
}
static DISP_STATUS dbi_init(UINT32 fbVA, UINT32 fbPA, BOOL isLcmInited)
{
if (!disp_drv_dbi_init_context())
return DISP_STATUS_NOT_IMPLEMENTED;
#if 0
#ifdef MT65XX_NEW_DISP
{
struct disp_path_config_struct config = { 0 };
config.srcModule = DISP_MODULE_OVL;
config.bgROI.x = 0;
config.bgROI.y = 0;
config.bgROI.width = DISP_GetScreenWidth();
config.bgROI.height = DISP_GetScreenHeight();
config.bgColor = 0x0; /* background color */
config.pitch = DISP_GetScreenWidth() * 2;
config.srcROI.x = 0;
config.srcROI.y = 0;
config.srcROI.height = DISP_GetScreenHeight();
config.srcROI.width = DISP_GetScreenWidth();
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
/* Config FB_Layer port to be physical. */
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_OVL_CH3; /* hardware port ID, defined in M4U_PORT_ID_ENUM */
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; /* domain : 0 1 2 3 */
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
/* Reconfig FB_Layer and enable it. */
config.ovl_config.layer = FB_LAYER;
config.ovl_config.layer_en = 1;
config.ovl_config.fmt = eRGB565;
config.ovl_config.addr = fbPA;
config.ovl_config.source = OVL_LAYER_SOURCE_MEM;
config.ovl_config.src_x = 0;
config.ovl_config.src_y = 0;
config.ovl_config.dst_x = 0; /* ROI */
config.ovl_config.dst_y = 0;
config.ovl_config.dst_w = DISP_GetScreenWidth();
config.ovl_config.dst_h = DISP_GetScreenHeight();
config.ovl_config.src_pitch = ALIGN_TO(DISP_GetScreenWidth(), 32) * 2;
config.ovl_config.keyEn = 0;
config.ovl_config.key = 0xFF; /* color key */
config.ovl_config.aen = 0; /* alpha enable */
config.ovl_config.alpha = 0;
LCD_LayerSetAddress(FB_LAYER, fbPA);
LCD_LayerSetFormat(FB_LAYER, LCD_LAYER_FORMAT_RGB565);
LCD_LayerSetOffset(FB_LAYER, 0, 0);
LCD_LayerSetSize(FB_LAYER, DISP_GetScreenWidth(), DISP_GetScreenHeight());
LCD_LayerSetPitch(FB_LAYER, ALIGN_TO(DISP_GetScreenWidth(), 32) * 2);
LCD_LayerEnable(FB_LAYER, TRUE);
config.dstModule = DISP_MODULE_DBI; /* DISP_MODULE_WDMA1 */
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
/* disp_path_get_mutex(); */
disp_path_config(&config);
/* Config LK UI layer port to be physical. */
{
M4U_PORT_STRUCT portStruct;
portStruct.ePortID = M4U_PORT_OVL_CH2; /* hardware port ID, defined in M4U_PORT_ID_ENUM */
portStruct.Virtuality = 1;
portStruct.Security = 0;
portStruct.domain = 3; /* domain : 0 1 2 3 */
portStruct.Distance = 1;
portStruct.Direction = 0;
m4u_config_port(&portStruct);
}
disp_bls_config();
}
#endif
init_io_pad();
init_io_driving_current();
init_lcd();
if (NULL != lcm_drv->init && !isLcmInited)
lcm_drv->init();
init_lcd_te_control();
DPI_PowerOn();
DPI_PowerOff();
DSI_PowerOn();
DSI_PowerOff();
#endif
return DISP_STATUS_OK;
}
int ddp_mem_test(void)
{
int result = 0;
struct disp_path_config_struct config;
unsigned int* pSrc;
unsigned char* pSrcPa;
unsigned int* pDst;
unsigned char* pDstPa;
pSrc= dma_alloc_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, (dma_addr_t *)&pSrcPa, GFP_KERNEL);
if(pSrc==0 || pSrcPa==0)
{
printk("dma_alloc_coherent error! dma memory not available.\n");
return 0;
}
else
{
printk("[ddp] pSrc=0x%x, pSrcPa=0x%x \n", (unsigned int)pSrc, (unsigned int)pSrcPa);
}
memcpy((void*)pSrc, data_rgb888_64x64, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
pDst= dma_alloc_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, (dma_addr_t *)&pDstPa, GFP_KERNEL);
if(pDst==0 || pDstPa==0)
{
printk("dma_alloc_coherent error! dma memory not available.\n");
return 0;
}
else
{
printk("[ddp] pDst=0x%x, pDstPa=0x%x \n",(unsigned int) pDst, (unsigned int)pDstPa);
}
memset((void*)pDst, 0, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP);
// config port to physical
{
M4U_PORT_STRUCT sPort;
sPort.ePortID = M4U_PORT_LCD_W;
sPort.Virtuality = 0;
sPort.Security = 0;
sPort.Distance = 1;
sPort.Direction = 0;
m4u_config_port(&sPort);
}
config.srcModule = DISP_MODULE_OVL;
config.addr = (unsigned int)pSrcPa;
config.inFormat = eRGB888;
config.pitch = DDP_TEST_WIDTH;
config.srcROI.x = 0;
config.srcROI.y = 0;
config.srcROI.width = DDP_TEST_WIDTH;
config.srcROI.height = DDP_TEST_HEIGHT;
config.srcWidth = DDP_TEST_WIDTH;
config.srcHeight = DDP_TEST_HEIGHT;
config.dstModule = DISP_MODULE_WDMA0;
config.outFormat = eRGB888;
config.dstAddr = (unsigned int)pDstPa;
config.dstWidth = DDP_TEST_WIDTH;
config.dstHeight = DDP_TEST_HEIGHT;
config.dstPitch = DDP_TEST_WIDTH;
/*
disp_power_on(DISP_MODULE_ROT);
disp_power_on(DISP_MODULE_SCL);
disp_power_on(DISP_MODULE_WDMA0);
*/
disp_path_get_mutex_(DDP_MUTEX_FOR_ROT_SCL_WDMA);
disp_path_config_(&config, DDP_MUTEX_FOR_ROT_SCL_WDMA);
printk("*after ddp test config start: -------------------\n");
disp_dump_reg(DISP_MODULE_OVL);
disp_dump_reg(DISP_MODULE_WDMA0);
disp_dump_reg(DISP_MODULE_CONFIG);
printk("*after ddp test config end: ---------------------\n");
disp_path_release_mutex_(DDP_MUTEX_FOR_ROT_SCL_WDMA);
if(*(volatile unsigned int*)DISP_REG_CONFIG_MUTEX1 != 0)
{
*(volatile unsigned int*)DISP_REG_CONFIG_MUTEX1 = 0;
}
printk("ddp_mem_test wdma wait done... \n");
WDMAWait(0);
printk("ddp_mem_test wdma done! \n");
if(0) //compare source
{
unsigned int diff_cnt = 0;
unsigned int t=0;
unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
for(t=0;t<size;t++)
{
if( *((unsigned char*)pSrc+t) != *((unsigned char*)data_rgb888_64x64+t) )
{
diff_cnt++;
printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
t,
diff_cnt,
*((unsigned char*)pSrc+t),
*((unsigned char*)data_rgb888_64x64+t) );
}
}
if(diff_cnt == 0)
printk("ddp_mem_test src compare result: success \n");
else
{
printk("ddp_mem_test src compare result: fail \n");
printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
result = -1;
}
}
if(1) //compare dst
{
unsigned int diff_cnt = 0;
unsigned int t=0;
unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
for(t=0;t<size;t++)
{
if( *((unsigned char*)pDst+t) != *((unsigned char*)data_rgb888_64x64_golden+t) )
{
diff_cnt++;
printk("t=%d, diff_cnt=%d, dst=0x%x, gold=0x%x \n",
t,
diff_cnt,
*((unsigned char*)pDst+t),
*((unsigned char*)data_rgb888_64x64_golden+t) );
}
}
if(diff_cnt == 0)
printk("ddp_mem_test result: success \n");
else
{
printk("ddp_mem_test result: fail \n");
printk("detail, %d, %d, %%%d \n", diff_cnt, size, diff_cnt*100/size);
result = -1;
}
}
// print out dst buffer to save as golden
if(0)
{
unsigned int t=0;
unsigned int size = DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP;
for(t=0;t<size;t++)
{
printk("0x%x, ", *((unsigned char*)pDst+t));
if((t+1)%12==0)
{
printk("\n%05d: ", (t+1)/12);
}
}
}
/*
disp_power_off(DISP_MODULE_ROT);
disp_power_off(DISP_MODULE_SCL);
disp_power_off(DISP_MODULE_WDMA0);
*/
//dealloc memory
dma_free_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, pSrc, (dma_addr_t)&pSrcPa);
dma_free_coherent(NULL, DDP_TEST_WIDTH*DDP_TEST_HEIGHT*DDP_TEST_BPP, pDst, (dma_addr_t)&pDstPa);
return result;
}