/**
* This function will initial board.
*/
void rt_hw_board_init()
{
// Configure the device for maximum performance, but do not change the PBDIV clock divisor.
// Given the options, this function will change the program Flash wait states,
// RAM wait state and enable prefetch cache, but will not change the PBDIV.
// The PBDIV value is already set via the pragma FPBDIV option above.
SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
/* use DBPRINTF */
/* rt_hw_console_init(); */
rt_hw_usart_init();
rt_console_set_device("uart1");
rt_hw_show_info();
// enable multi-vector interrupts
INTEnableSystemMultiVectoredInt();
rt_hw_interrupt_disable();
// // STEP 2. configure the core timer
// OpenCoreTimer(CORE_TICK_RATE);
//
// // set up the core timer interrupt with a prioirty of 2 and zero sub-priority
// mConfigIntCoreTimer((CT_INT_ON | CT_INT_PRIOR_2 | CT_INT_SUB_PRIOR_0));
// STEP 2. configure Timer 1 using internal clock, 1:256 prescale
OpenTimer1(T1_ON | T1_SOURCE_INT | T1_PS_1_256, T1_TICK);
// set up the timer interrupt with a priority of 2
ConfigIntTimer1(T1_INT_ON | T1_INT_PRIOR_2);
/* Setup the software interrupt. */
mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
}
portBASE_TYPE xPortStartScheduler( void )
{
extern void vPortStartFirstTask( void );
extern void *pxCurrentTCB;
/* Setup the software interrupt. */
mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
/* Setup the timer to generate the tick. Interrupts will have been
disabled by the time we get here. */
prvSetupTimerInterrupt();
/* Kick off the highest priority task that has been created so far.
Its stack location is loaded into uxSavedTaskStackPointer. */
uxSavedTaskStackPointer = *( unsigned portBASE_TYPE * ) pxCurrentTCB;
vPortStartFirstTask();
/* Should never get here as the tasks will now be executing. */
return pdFALSE;
}
