void pit68230_device::wr_pitreg_pacr(uint8_t data)
{
LOG("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, tag(), FUNCNAME, data);
LOGSETUP("%s PACR", tag());
m_pacr = data;
// callbacks
/*PACR in Mode 0
* 5 43 H2 Control in Submode 00 && 01
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 00 Output pin - negated, H2S is always clear.
* 1 01 Output pin - asserted, H2S is always clear.
* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
*
* 5 43 H2 Control in Submode 1x
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 X0 Output pin - negated, H2S is always cleared.
* 1 X1 Output pin - asserted, H2S is always cleared.
*/
if (m_pgcr & REG_PGCR_H12_ENABLE)
{
if (m_pacr & REG_PACR_H2_CTRL_IN_OUT)
{
switch(m_pacr & REG_PACR_H2_CTRL_MASK)
{
case REG_PACR_H2_CTRL_OUT_00:
LOGSETUP(" - H2 cleared\n");
m_h2_out_cb(CLEAR_LINE);
break;
case REG_PACR_H2_CTRL_OUT_01:
LOGSETUP(" - H2 asserted\n");
m_h2_out_cb(ASSERT_LINE);
break;
case REG_PACR_H2_CTRL_OUT_10:
LOGSETUP(" - interlocked handshake not implemented\n");
break;
case REG_PACR_H2_CTRL_OUT_11:
LOGSETUP(" - pulsed handshake not implemented\n");
break;
default: logerror(("Undefined H2 mode, broken driver - please report!\n"));
}
}
}
else
{
LOGSETUP(" - H2 cleared because being disabled in PGCR\n");
m_h2_out_cb(CLEAR_LINE);
}
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void pit68230_device::device_reset ()
{
LOG(("%s %s \n",tag(), FUNCNAME));
m_pgcr = 0;
m_psrr = 0;
m_paddr = 0;
m_pbddr = 0;
m_pcddr = 0;
m_pacr = 0; m_h2_out_cb(m_pacr);
m_pbcr = 0;
m_padr = 0; m_pa_out_cb((offs_t)0, m_padr); // TODO: check PADDR
m_pbdr = 0;
m_psr = 0;
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void pit68230_device::device_reset ()
{
LOGSETUP("%s %s \n",tag(), FUNCNAME);
m_pgcr = 0;
m_psrr = 0;
m_paddr = 0;
m_pbddr = 0;
m_pcddr = 0;
m_pivr = 0x0f; m_pirq_out_cb(CLEAR_LINE);
m_pacr = 0; m_h2_out_cb(CLEAR_LINE);
m_pbcr = 0; m_h4_out_cb(CLEAR_LINE);
m_padr = 0; m_pa_out_cb((offs_t)0, m_padr);
m_pbdr = 0; m_pb_out_cb((offs_t)0, m_pbdr);
m_pcdr = 0; m_pc_out_cb((offs_t)0, m_pcdr);
m_psr = 0;
m_tcr = 0;
m_tivr = 0x0f; m_tirq_out_cb(CLEAR_LINE);
m_tsr = 0;
LOGSETUP("%s %s DONE!\n",tag(), FUNCNAME);
}
void pit68230_device::wr_pitreg_pacr(UINT8 data)
{
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
m_pacr = data;
// callbacks
/*PACR in Mode 0
* 5 43 H2 Control in Submode 00 && 01
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 00 Output pin - negated, H2S is always clear.
* 1 01 Output pin - asserted, H2S is always clear.
* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
*
* 5 43 H2 Control in Submode 1x
* ------------------------------------
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
* 1 X0 Output pin - negated, H2S is always cleared.
* 1 X1 Output pin - asserted, H2S is always cleared.
*/
m_h2_out_cb (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
}
