/* ----------------------------------------------------------------------------
nmclan_reset
Reset and restore all of the Xilinx and MACE registers.
---------------------------------------------------------------------------- */
static void nmclan_reset(struct net_device *dev)
{
mace_private *lp = netdev_priv(dev);
#if RESET_XILINX
struct pcmcia_device *link = &lp->link;
u8 OrigCorValue;
/* Save original COR value */
pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
/* Reset Xilinx */
dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
OrigCorValue);
pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
/* Need to wait for 20 ms for PCMCIA to finish reset. */
/* Restore original COR configuration index */
pcmcia_write_config_byte(link, CISREG_COR,
(COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
/* Xilinx is now completely reset along with the MACE chip. */
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
#endif /* #if RESET_XILINX */
/* Xilinx is now completely reset along with the MACE chip. */
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
/* Reinitialize the MACE chip for operation. */
mace_init(lp, dev->base_addr, dev->dev_addr);
mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
/* Restore the multicast list and enable TX and RX. */
restore_multicast_list(dev);
} /* nmclan_reset */
/* ----------------------------------------------------------------------------
nmclan_reset
Reset and restore all of the Xilinx and MACE registers.
---------------------------------------------------------------------------- */
static void nmclan_reset(struct net_device *dev)
{
mace_private *lp = netdev_priv(dev);
#if RESET_XILINX
struct pcmcia_device *link = &lp->link;
conf_reg_t reg;
u_long OrigCorValue;
/* Save original COR value */
reg.Function = 0;
reg.Action = CS_READ;
reg.Offset = CISREG_COR;
reg.Value = 0;
pcmcia_access_configuration_register(link, ®);
OrigCorValue = reg.Value;
/* Reset Xilinx */
reg.Action = CS_WRITE;
reg.Offset = CISREG_COR;
DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
OrigCorValue);
reg.Value = COR_SOFT_RESET;
pcmcia_access_configuration_register(link, ®);
/* Need to wait for 20 ms for PCMCIA to finish reset. */
/* Restore original COR configuration index */
reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
pcmcia_access_configuration_register(link, ®);
/* Xilinx is now completely reset along with the MACE chip. */
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
#endif /* #if RESET_XILINX */
/* Xilinx is now completely reset along with the MACE chip. */
lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
/* Reinitialize the MACE chip for operation. */
mace_init(lp, dev->base_addr, dev->dev_addr);
mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
/* Restore the multicast list and enable TX and RX. */
restore_multicast_list(dev);
} /* nmclan_reset */
/* ----------------------------------------------------------------------------
mace_init
Resets the MACE chip.
---------------------------------------------------------------------------- */
static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
{
int i;
int ct = 0;
/* MACE Software reset */
mace_write(lp, ioaddr, MACE_BIUCC, 1);
while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
/* Wait for reset bit to be cleared automatically after <= 200ns */;
if(++ct > 500)
{
printk(KERN_ERR "mace: reset failed, card removed ?\n");
return -1;
}
udelay(1);
}
mace_write(lp, ioaddr, MACE_BIUCC, 0);
/* The Am2150 requires that the MACE FIFOs operate in burst mode. */
mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
/*
* Bit 2-1 PORTSEL[1-0] Port Select.
* 00 AUI/10Base-2
* 01 10Base-T
* 10 DAI Port (reserved in Am2150)
* 11 GPSI
* For this card, only the first two are valid.
* So, PLSCC should be set to
* 0x00 for 10Base-2
* 0x02 for 10Base-T
* Or just set ASEL in PHYCC below!
*/
switch (if_port) {
case 1:
mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
break;
case 2:
mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
break;
default:
mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
/* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
and the MACE device will automatically select the operating media
interface port. */
break;
}
mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
/* Poll ADDRCHG bit */
ct = 0;
while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
{
if(++ ct > 500)
{
printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
return -1;
}
}
/* Set PADR register */
for (i = 0; i < ETHER_ADDR_LEN; i++)
mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
/* MAC Configuration Control Register should be written last */
/* Let set_multicast_list set this. */
/* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
mace_write(lp, ioaddr, MACE_MACCC, 0x00);
return 0;
} /* mace_init */
