/* Initialization routine for secondary CPUs after they are brought out of * reset. */ void platform_secondary_init(unsigned int cpu) { printk(KERN_DEBUG "%s: cpu:%d\n", __func__, cpu); #ifdef CONFIG_HOTPLUG_CPU WARN_ON(msm_pm_platform_secondary_init(cpu)); #endif trace_hardirqs_off(); /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); /* RUMI does not adhere to GIC spec by enabling STIs by default. * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. */ if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() || machine_is_msm8x60_rumi3()) writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); /* * setup GIC (GIC number NOT CPU number and the base address of the * GIC CPU interface */ gic_cpu_init(0, MSM_QGIC_CPU_BASE); }
void platform_secondary_init(unsigned int cpu) { printk(KERN_DEBUG "%s: cpu:%d\n", __func__, cpu); trace_hardirqs_off(); writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() || machine_is_msm8x60_rumi3()) writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); gic_cpu_init(0, MSM_QGIC_CPU_BASE); }