static void test_config_parse_capability_set(void) {
/* int config_parse_capability_set(
const char *unit,
const char *filename,
unsigned line,
const char *section,
unsigned section_line,
const char *lvalue,
int ltype,
const char *rvalue,
void *data,
void *userdata) */
int r;
uint64_t capability_bounding_set = 0;
r = config_parse_capability_set(NULL, "fake", 1, "section", 1,
"CapabilityBoundingSet", 0, "CAP_NET_RAW",
&capability_bounding_set, NULL);
assert_se(r >= 0);
assert_se(capability_bounding_set == make_cap(CAP_NET_RAW));
r = config_parse_capability_set(NULL, "fake", 1, "section", 1,
"CapabilityBoundingSet", 0, "CAP_NET_ADMIN",
&capability_bounding_set, NULL);
assert_se(r >= 0);
assert_se(capability_bounding_set == (make_cap(CAP_NET_RAW) | make_cap(CAP_NET_ADMIN)));
r = config_parse_capability_set(NULL, "fake", 1, "section", 1,
"CapabilityBoundingSet", 0, "",
&capability_bounding_set, NULL);
assert_se(r >= 0);
assert_se(capability_bounding_set == UINT64_C(0));
r = config_parse_capability_set(NULL, "fake", 1, "section", 1,
"CapabilityBoundingSet", 0, "~",
&capability_bounding_set, NULL);
assert_se(r >= 0);
assert_se(cap_test_all(capability_bounding_set));
capability_bounding_set = 0;
r = config_parse_capability_set(NULL, "fake", 1, "section", 1,
"CapabilityBoundingSet", 0, " 'CAP_NET_RAW' WAT_CAP??? CAP_NET_ADMIN CAP'_trailing_garbage",
&capability_bounding_set, NULL);
assert_se(r >= 0);
assert_se(capability_bounding_set == (make_cap(CAP_NET_RAW) | make_cap(CAP_NET_ADMIN)));
}
}
char data[30];
//=========================================
tmr16_int_reg_t tir4 = make_tir(4);
coil_ch_act_t t4ch3 = make_coil_ch(4C, tir4, NULL);
coil_ch_act_t t4ch2 = make_coil_ch(4B, tir4, &t4ch3);
coil_ch_act_t t4ch1 = make_coil_ch(4A, tir4, &t4ch2);
tmr16_ctrl_reg_t tcr4 = make_tcr(4);
tmr16_ctrl_mask_t tcs4 = make_cs8_mask(4, tcr4);
tmr16_ctrl_mask_t tcnt4_mask = make_tcnt_mask(0, tcr4);
tmr16_int_reg_t tir5 = make_tir(5);
tmr16_int_ctrl_t cap5 = make_cap(5, tir5);
tmr16_int_ctrl_t cha5 = make_ch(5A, tir5);
tmr16_int_ctrl_t chb5 = make_ch(5B, tir5);
tmr16_int_ctrl_t chc5 = make_ch(5C, tir5);
tmr16_int_ctrl_t ovf5 = make_ovf(5, tir5);
tmr16_ctrl_reg_t tcr5 = make_tcr(5);
tmr16_ctrl_mask_t tcs5 = make_cs8_mask(5, tcr5);
tmr16_ctrl_mask_t tcnt5_mask = make_tcnt_mask(0, tcr5);
tmr16_ctrl_mask_t cap5_pos_mask = {
.ctrl_reg = &tcr5,
.mask = (1 << ICES5),
};
ISR(TIMER4_COMPA_vect) { //coil interrupt
coil_call_event_once(&t4ch1);
if (uart_tx_done(&uart0)) {
