void mali_gp_update_performance_counters(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 val0 = 0;
u32 val1 = 0;
u32 counter_src0 = mali_gp_job_get_perf_counter_src0(job);
u32 counter_src1 = mali_gp_job_get_perf_counter_src1(job);
if (MALI_HW_CORE_NO_COUNTER != counter_src0) {
val0 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
mali_gp_job_set_perf_counter_value0(job, val0);
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_report_hw_counter(COUNTER_VP_0_C0, val0);
#endif
}
if (MALI_HW_CORE_NO_COUNTER != counter_src1) {
val1 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
mali_gp_job_set_perf_counter_value1(job, val1);
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_report_hw_counter(COUNTER_VP_0_C1, val1);
#endif
}
}
void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 startcmd = 0;
u32 *frame_registers = mali_gp_job_get_frame_registers(job);
core->counter_src0_used = mali_gp_job_get_perf_counter_src0(job);
core->counter_src1_used = mali_gp_job_get_perf_counter_src1(job);
MALI_DEBUG_ASSERT_POINTER(core);
if (mali_gp_job_has_vs_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
}
if (mali_gp_job_has_plbu_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
}
MALI_DEBUG_ASSERT(0 != startcmd);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
}
void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 startcmd = 0;
u32 *frame_registers = mali_gp_job_get_frame_registers(job);
u32 counter_src0 = mali_gp_job_get_perf_counter_src0(job);
u32 counter_src1 = mali_gp_job_get_perf_counter_src1(job);
MALI_DEBUG_ASSERT_POINTER(core);
if (mali_gp_job_has_vs_job(job)) {
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
}
if (mali_gp_job_has_plbu_job(job)) {
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
}
MALI_DEBUG_ASSERT(0 != startcmd);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
if (MALI_HW_CORE_NO_COUNTER != counter_src0) {
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, counter_src0);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != counter_src1) {
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, counter_src1);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_UPDATE_PLBU_ALLOC);
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core.
*
* Don't actually run the job if PROFILING_SKIP_PP_JOBS are set, just
* force core to assert the completion interrupt.
*/
#if !defined(PROFILING_SKIP_GP_JOBS)
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
#else
{
u32 bits = 0;
if (mali_gp_job_has_vs_job(job))
bits = MALIGP2_REG_VAL_IRQ_VS_END_CMD_LST;
if (mali_gp_job_has_plbu_job(job))
bits |= MALIGP2_REG_VAL_IRQ_PLBU_END_CMD_LST;
mali_hw_core_register_write_relaxed(&core->hw_core,
MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT, bits);
}
#endif
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
}
static void mali_gp_post_process_job(struct mali_gp_core *core, mali_bool suspend)
{
MALI_ASSERT_GROUP_LOCKED(core->group);
if (NULL != core->running_job)
{
u32 val0 = 0;
u32 val1 = 0;
#if MALI_TIMELINE_PROFILING_ENABLED
u32 event_id;
#endif
#if PROFILING_PRINT_L2_HITRATE_ON_GP_FINISH
{
u32 src0, value0, src1, value1, sum, per_thousand, per_thousand_now, diff0, diff1;
static u32 print_nr=0;
static u32 prev0=0;
static u32 prev1=0;
if ( !(++print_nr&511) )
{
mali_l2_cache_core_get_counter_values(mali_l2_cache_core_get_glob_l2_core(0), &src0, &value0, &src1, &value1);
MALI_DEBUG_ASSERT( src0==20 );
MALI_DEBUG_ASSERT( src1==21 );
sum = value0+value1;
if ( sum > 1000000 )
{
per_thousand = value0 / (sum/1000);
}
else
{
per_thousand = (value0*1000) / (sum);
}
diff0 = value0-prev0;
diff1 = value1-prev1;
sum = diff0 + diff1 ;
if ( sum > 1000000 )
{
per_thousand_now = diff0 / (sum/1000);
}
else
{
per_thousand_now = (diff0*1000) / (sum);
}
prev0=value0;
prev1=value1;
if (per_thousand_now<=1000)
{
MALI_DEBUG_PRINT(2, ("Mali L2: Read hits/misses: %d/%d = %d thousand_parts total, since previous: %d\n", value0, value1, per_thousand, per_thousand_now));
}
}
}
#endif
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
val0 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
if (mali_gp_job_get_perf_counter_flag(core->running_job) &&
_MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE && mali_gp_job_get_perf_counter_src0(core->running_job) == core->counter_src0_used)
{
mali_gp_job_set_perf_counter_value0(core->running_job, val0);
}
else
{
mali_gp_job_set_perf_counter_value0(core->running_job, MALI_HW_CORE_INVALID_VALUE);
}
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_report_hw_counter(COUNTER_VP_C0, val0);
#endif
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
val1 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
if (mali_gp_job_get_perf_counter_flag(core->running_job) &&
_MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE && mali_gp_job_get_perf_counter_src1(core->running_job) == core->counter_src1_used)
{
mali_gp_job_set_perf_counter_value1(core->running_job, val1);
}
else
{
mali_gp_job_set_perf_counter_value1(core->running_job, MALI_HW_CORE_INVALID_VALUE);
}
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_report_hw_counter(COUNTER_VP_C1, val1);
#endif
}
#if MALI_TIMELINE_PROFILING_ENABLED
if (MALI_TRUE == suspend)
{
event_id = MALI_PROFILING_EVENT_TYPE_SUSPEND|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0);
}
else
{
event_id = MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0);
}
_mali_osk_profiling_add_event(event_id, val0, val1, core->counter_src0_used | (core->counter_src1_used << 8), 0, 0);
#endif
mali_gp_job_set_current_heap_addr(core->running_job,
mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR));
if (MALI_TRUE != suspend)
{
core->running_job = NULL;
_mali_osk_timer_del(core->timeout_timer);
}
}
}
void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 startcmd = 0;
u32 *frame_registers = mali_gp_job_get_frame_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
if (mali_gp_job_has_vs_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
}
if (mali_gp_job_has_plbu_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
}
MALI_DEBUG_ASSERT(0 != startcmd);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
#if PROFILING_PRINT_L2_HITRATE_ON_GP_FINISH
{
mali_l2_cache_core_set_counter_src0(mali_l2_cache_core_get_glob_l2_core(0), 20);
mali_l2_cache_core_set_counter_src1(mali_l2_cache_core_get_glob_l2_core(0), 21);
}
#endif
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
else
{
u32 perf_counter_flag = mali_gp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_gp_job_get_perf_counter_src0(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_gp_job_get_perf_counter_src1(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
_mali_osk_write_mem_barrier();
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
_mali_osk_write_mem_barrier();
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_gp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH,
job->frame_builder_id, job->flush_id, 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0), job->pid, job->tid, 0, 0, 0);
#endif
core->running_job = job;
}
void mali_gp_job_start(struct mali_gp_core *core, struct mali_gp_job *job)
{
u32 startcmd = 0;
u32 *frame_registers = mali_gp_job_get_frame_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
if (mali_gp_job_has_vs_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_VS;
}
if (mali_gp_job_has_plbu_job(job))
{
startcmd |= (u32) MALIGP2_REG_VAL_CMD_START_PLBU;
}
MALI_DEBUG_ASSERT(0 != startcmd);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_VSCL_START_ADDR, frame_registers, MALIGP2_NUM_REGS_FRAME);
#if PROFILING_PRINT_L2_HITRATE_ON_GP_FINISH
{
/* Read hits and Read misses*/
mali_l2_cache_core_set_counter_src0(mali_l2_cache_core_get_glob_l2_core(0), 20);
mali_l2_cache_core_set_counter_src1(mali_l2_cache_core_get_glob_l2_core(0), 21);
}
#endif
/* This selects which performance counters we are reading */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
/* global_config has enabled HW counters, this will override anything specified by user space */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
else
{
/* Use HW counters from job object, if any */
u32 perf_counter_flag = mali_gp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_gp_job_get_perf_counter_src0(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_gp_job_get_perf_counter_src1(job);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALIGP2_REG_VAL_PERF_CNT_ENABLE);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali GP: Starting job (0x%08x) on core %s with command 0x%08X\n", job, core->hw_core.description, startcmd));
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, startcmd);
/* Barrier to make sure the previous register write is finished */
_mali_osk_write_mem_barrier();
/* Setup the timeout timer value and save the job id for the job running on the gp core */
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_gp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH,
mali_gp_job_get_frame_builder_id(job), mali_gp_job_get_flush_id(job), 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0), mali_gp_job_get_pid(job), mali_gp_job_get_tid(job), 0, 0, 0);
#endif
core->running_job = job;
}
static void mali_gp_post_process_job(struct mali_gp_core *core, mali_bool suspend)
{
MALI_ASSERT_GROUP_LOCKED(core->group);
if (NULL != core->running_job)
{
u32 val0 = 0;
u32 val1 = 0;
#if MALI_TIMELINE_PROFILING_ENABLED
u32 event_id;
#endif
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
val0 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_0_VALUE);
if (mali_gp_job_get_perf_counter_flag(core->running_job) &&
_MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE && mali_gp_job_get_perf_counter_src0(core->running_job) == core->counter_src0_used)
{
/* We retrieved the counter that user space asked for, so return the value through the job object */
mali_gp_job_set_perf_counter_value0(core->running_job, val0);
}
else
{
/* User space asked for a counter, but this is not what we retrived (overridden by counter src set on core) */
mali_gp_job_set_perf_counter_value0(core->running_job, MALI_HW_CORE_INVALID_VALUE);
}
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_report_hw_counter(COUNTER_VP_C0, val0);
#endif
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
val1 = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PERF_CNT_1_VALUE);
if (mali_gp_job_get_perf_counter_flag(core->running_job) &&
_MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE && mali_gp_job_get_perf_counter_src1(core->running_job) == core->counter_src1_used)
{
/* We retrieved the counter that user space asked for, so return the value through the job object */
mali_gp_job_set_perf_counter_value1(core->running_job, val1);
}
else
{
/* User space asked for a counter, but this is not what we retrieved (overridden by counter src set on core) */
mali_gp_job_set_perf_counter_value1(core->running_job, MALI_HW_CORE_INVALID_VALUE);
}
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_report_hw_counter(COUNTER_VP_C1, val1);
#endif
}
#if MALI_TIMELINE_PROFILING_ENABLED
if (MALI_TRUE == suspend)
{
event_id = MALI_PROFILING_EVENT_TYPE_SUSPEND|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0);
}
else
{
event_id = MALI_PROFILING_EVENT_TYPE_STOP|MALI_PROFILING_MAKE_EVENT_CHANNEL_GP(0);
}
_mali_osk_profiling_add_event(event_id, val0, val1, core->counter_src0_used | (core->counter_src1_used << 8), 0, 0);
#endif
mali_gp_job_set_current_heap_addr(core->running_job,
mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR));
if (MALI_TRUE != suspend)
{
/* We are no longer running a job... */
core->running_job = NULL;
_mali_osk_timer_del(core->timeout_timer);
}
}
}
