static void mali_pp_scheduler_return_job_to_user(struct mali_pp_job *job)
{
if (MALI_FALSE == mali_pp_job_use_no_notification(job))
{
_mali_osk_notification_t *notobj = _mali_osk_notification_create(_MALI_NOTIFICATION_PP_FINISHED, sizeof(_mali_uk_pp_job_finished_s));
if (NULL != notobj)
{
u32 i;
u32 sub_jobs = mali_pp_job_get_sub_job_count(job);
mali_bool success = mali_pp_job_was_success(job);
_mali_uk_pp_job_finished_s *jobres = notobj->result_buffer;
_mali_osk_memset(jobres, 0, sizeof(_mali_uk_pp_job_finished_s)); /* @@@@ can be removed once we initialize all members in this struct */
jobres->user_job_ptr = mali_pp_job_get_user_id(job);
if (MALI_TRUE == success)
{
jobres->status = _MALI_UK_JOB_STATUS_END_SUCCESS;
}
else
{
jobres->status = _MALI_UK_JOB_STATUS_END_UNKNOWN_ERR;
}
for (i = 0; i < sub_jobs; i++)
{
jobres->perf_counter0[i] = mali_pp_job_get_perf_counter_value0(job, i);
jobres->perf_counter1[i] = mali_pp_job_get_perf_counter_value1(job, i);
}
mali_session_send_notification(mali_pp_job_get_session(job), notobj);
}
else
{
MALI_PRINT_ERROR(("Mali PP scheduler: Unable to allocate notification object\n"));
}
}
mali_pp_job_delete(job);
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job, mali_bool restart_virtual)
{
u32 relative_address;
u32 start_index;
u32 nr_of_regs;
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
u32 counter_src0 = mali_pp_job_get_perf_counter_src0(job, sub_job);
u32 counter_src1 = mali_pp_job_get_perf_counter_src1(job, sub_job);
MALI_DEBUG_ASSERT_POINTER(core);
/* Write frame registers */
/*
* There are two frame registers which are different for each sub job:
* 1. The Renderer List Address Register (MALI200_REG_ADDR_FRAME)
* 2. The FS Stack Address Register (MALI200_REG_ADDR_STACK)
*/
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_FRAME / sizeof(u32)]);
/* For virtual jobs, the stack address shouldn't be broadcast but written individually */
if (!mali_pp_job_is_virtual(job) || restart_virtual) {
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_STACK / sizeof(u32)]);
}
/* Write registers between MALI200_REG_ADDR_FRAME and MALI200_REG_ADDR_STACK */
relative_address = MALI200_REG_ADDR_RSW;
start_index = MALI200_REG_ADDR_RSW / sizeof(u32);
nr_of_regs = (MALI200_REG_ADDR_STACK - MALI200_REG_ADDR_RSW) / sizeof(u32);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core,
relative_address, &frame_registers[start_index],
nr_of_regs, &mali_frame_registers_reset_values[start_index]);
/* MALI200_REG_ADDR_STACK_SIZE */
relative_address = MALI200_REG_ADDR_STACK_SIZE;
start_index = MALI200_REG_ADDR_STACK_SIZE / sizeof(u32);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core,
relative_address, frame_registers[start_index],
mali_frame_registers_reset_values[start_index]);
/* Skip 2 reserved registers */
/* Write remaining registers */
relative_address = MALI200_REG_ADDR_ORIGIN_OFFSET_X;
start_index = MALI200_REG_ADDR_ORIGIN_OFFSET_X / sizeof(u32);
nr_of_regs = MALI_PP_MALI400_NUM_FRAME_REGISTERS - MALI200_REG_ADDR_ORIGIN_OFFSET_X / sizeof(u32);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core,
relative_address, &frame_registers[start_index],
nr_of_regs, &mali_frame_registers_reset_values[start_index]);
/* Write WBx registers */
if (wb0_registers[0]) { /* M200_WB0_REG_SOURCE_SELECT register */
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (wb1_registers[0]) { /* M200_WB1_REG_SOURCE_SELECT register */
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (wb2_registers[0]) { /* M200_WB2_REG_SOURCE_SELECT register */
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (MALI_HW_CORE_NO_COUNTER != counter_src0) {
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, counter_src0);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (MALI_HW_CORE_NO_COUNTER != counter_src1) {
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, counter_src1);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
#ifdef CONFIG_MALI400_HEATMAPS_ENABLED
if (job->uargs.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_HEATMAP_ENABLE) {
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERFMON_CONTR, ((job->uargs.tilesx & 0x3FF) << 16) | 1);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERFMON_BASE, job->uargs.heatmap_mem & 0xFFFFFFF8);
}
#endif /* CONFIG_MALI400_HEATMAPS_ENABLED */
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
/* Adding barrier to make sure all rester writes are finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core.
*
* Don't actually run the job if PROFILING_SKIP_PP_JOBS are set, just
* force core to assert the completion interrupt.
*/
#if !defined(PROFILING_SKIP_PP_JOBS)
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
#else
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT, MALI200_REG_VAL_IRQ_END_OF_FRAME);
#endif
/* Adding barrier to make sure previous rester writes is finished */
_mali_osk_write_mem_barrier();
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job)
{
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_FRAME, frame_registers, MALI200_NUM_REGS_FRAME, mali_frame_registers_reset_values);
_mali_osk_mem_barrier();
if (0 != sub_job)
{
/*
* There are two frame registers which are different for each sub job.
* For the first sub job, these are correctly represented in the frame register array,
* but we need to patch these for all other sub jobs
*/
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job));
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_STACK/4]);
}
if (wb0_registers[0]) /* M200_WB0_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, 0, mali_wb_registers_reset_values[0] );
}
if (wb1_registers[0]) /* M200_WB1_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, 0, mali_wb_registers_reset_values[0] );
}
if (wb2_registers[0]) /* M200_WB2_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, 0, mali_wb_registers_reset_values[0] );
}
/* This selects which performance counters we are reading */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
/* global_config has enabled HW counters, this will override anything specified by user space */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
}
else
{
/* Use HW counters from job object, if any */
u32 perf_counter_flag = mali_pp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_pp_job_get_perf_counter_src0(job);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_pp_job_get_perf_counter_src1(job);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
/* Adding barrier to make sure all rester writes are finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
/* Adding barrier to make sure previous rester writes is finished */
_mali_osk_write_mem_barrier();
/* Setup the timeout timer value and save the job id for the job running on the pp core */
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_pp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH, mali_pp_job_get_frame_builder_id(job), mali_pp_job_get_flush_id(job), 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id), mali_pp_job_get_pid(job), mali_pp_job_get_tid(job), 0, 0, 0);
#endif
core->running_job = job;
core->running_sub_job = sub_job;
}
_mali_osk_errcode_t _mali_ukk_pp_start_job(_mali_uk_pp_start_job_s *args)
{
struct mali_session_data *session;
struct mali_pp_job *job;
MALI_DEBUG_ASSERT_POINTER(args);
MALI_DEBUG_ASSERT_POINTER(args->ctx);
session = (struct mali_session_data*)args->ctx;
job = mali_pp_job_create(session, args, mali_scheduler_get_new_id());
if (NULL == job)
{
return _MALI_OSK_ERR_NOMEM;
}
if (_MALI_OSK_ERR_OK != mali_pp_job_check(job))
{
/* Not a valid job, return to user immediately */
mali_pp_job_mark_sub_job_completed(job, MALI_FALSE); /* Flagging the job as failed. */
mali_pp_scheduler_return_job_to_user(job); /* This will also delete the job object */
return _MALI_OSK_ERR_OK; /* User is notified via a notification, so this call is ok */
}
#if PROFILING_SKIP_PP_JOBS || PROFILING_SKIP_PP_AND_GP_JOBS
#warning PP jobs will not be executed
mali_pp_scheduler_return_job_to_user(job);
return _MALI_OSK_ERR_OK;
#endif
mali_pp_scheduler_lock();
_mali_osk_list_addtail(&job->list, &job_queue);
MALI_DEBUG_PRINT(3, ("Mali PP scheduler: Job %u (0x%08X) with %u parts queued\n", mali_pp_job_get_id(job), job, mali_pp_job_get_sub_job_count(job)));
mali_pp_scheduler_schedule();
mali_pp_scheduler_unlock();
return _MALI_OSK_ERR_OK;
}
void mali_pp_scheduler_job_done(struct mali_group *group, struct mali_pp_job *job, u32 sub_job, mali_bool success)
{
u32 i;
mali_bool job_is_done;
MALI_DEBUG_PRINT(3, ("Mali PP scheduler: Job %u (0x%08X) part %u/%u completed (%s)\n", mali_pp_job_get_id(job), job, sub_job + 1, mali_pp_job_get_sub_job_count(job), success ? "success" : "failure"));
mali_pp_scheduler_lock();
/* Find slot which was running this job */
for (i = 0; i < num_slots; i++)
{
if (slots[i].group == group)
{
MALI_DEBUG_ASSERT(MALI_PP_SLOT_STATE_WORKING == slots[i].state);
slots[i].state = MALI_PP_SLOT_STATE_IDLE;
slots[i].session = NULL;
num_slots_idle++;
mali_pp_job_mark_sub_job_completed(job, success);
}
}
/* If paused, then this was the last job, so wake up sleeping workers */
if (pause_count > 0)
{
/* Wake up sleeping workers. Their wake-up condition is that
* num_slots == num_slots_idle, so unless we are done working, no
* threads will actually be woken up.
*/
_mali_osk_wait_queue_wake_up(pp_scheduler_working_wait_queue);
}
else
{
mali_pp_scheduler_schedule();
}
job_is_done = mali_pp_job_is_complete(job);
mali_pp_scheduler_unlock();
if (job_is_done)
{
/* Send notification back to user space */
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: All parts completed for job %u (0x%08X)\n", mali_pp_job_get_id(job), job));
mali_pp_scheduler_return_job_to_user(job);
}
}
static void mali_pp_scheduler_schedule(void)
{
u32 i;
struct mali_pp_job *job;
#if MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS
struct mali_session_data * session;
#endif
MALI_ASSERT_PP_SCHEDULER_LOCKED();
if (0 < pause_count || 0 == num_slots_idle || _mali_osk_list_empty(&job_queue))
{
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: Nothing to schedule (paused=%u, idle slots=%u)\n",
pause_count, num_slots_idle));
return; /* Nothing to do, so early out */
}
#if MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP
if ( num_slots_idle < num_slots )
{
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: Job not started, since only %d/%d cores are available\n", num_slots_idle,num_slots));
return;
}
#endif
#if MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS
/* Finding initial session for the PP cores */
job = _MALI_OSK_LIST_ENTRY(job_queue.next, struct mali_pp_job, list);
session = job->session;
if ( num_slots != num_slots_idle )
{
for (i = 0; (i < num_slots) ; i++)
{
if ( slots[i].state == MALI_PP_SLOT_STATE_IDLE )
{
continue;
}
session = mali_group_get_session(slots[i].group);
break;
}
}
#endif
for (i = 0; (i < num_slots) && (0 < num_slots_idle); i++)
{
u32 sub_job;
if (_mali_osk_list_empty(&job_queue)) /* move this check down to where we know we have started all sub jobs for this job??? */
{
break; /* No more jobs to schedule, so early out */
}
if (MALI_PP_SLOT_STATE_IDLE != slots[i].state)
{
continue;
}
job = _MALI_OSK_LIST_ENTRY(job_queue.next, struct mali_pp_job, list);
MALI_DEBUG_ASSERT(mali_pp_job_has_unstarted_sub_jobs(job)); /* All jobs on the job_queue should have unstarted sub jobs */
if (MALI_TRUE == mali_pp_job_has_active_barrier(job))
{
if (MALI_TRUE == mali_pp_scheduler_session_has_running_jobs(mali_pp_job_get_session(job)))
{
/* There is already a running job from this session, so we need to enforce the barrier */
return;
}
else
{
/* Barrier is now enforced, update job object so we don't delay execution of sub-jobs */
mali_pp_job_barrier_enforced(job);
}
}
#if MALI_PP_SCHEDULER_KEEP_SUB_JOB_STARTS_ALIGNED
if ( (0==job->sub_jobs_started) && (num_slots_idle < num_slots) && (job->sub_job_count > num_slots_idle))
{
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: Job with %d subjobs not started, since only %d/%d cores are available\n", job->sub_job_count, num_slots_idle,num_slots));
return;
}
#endif
#if MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP_BETWEEN_APPS
if ( job->session != session )
{
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: Job not started since existing job is from another application\n"));
return;
}
#endif
sub_job = mali_pp_job_get_first_unstarted_sub_job(job);
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: Starting job %u (0x%08X) part %u/%u\n", mali_pp_job_get_id(job), job, sub_job + 1, mali_pp_job_get_sub_job_count(job)));
if (_MALI_OSK_ERR_OK == mali_group_start_pp_job(slots[i].group, job, sub_job))
{
MALI_DEBUG_PRINT(4, ("Mali PP scheduler: Job %u (0x%08X) part %u/%u started\n", mali_pp_job_get_id(job), job, sub_job + 1, mali_pp_job_get_sub_job_count(job)));
/* Mark this sub job as started */
mali_pp_job_mark_sub_job_started(job, sub_job);
/* Mark slot as busy */
slots[i].state = MALI_PP_SLOT_STATE_WORKING;
slots[i].session = mali_pp_job_get_session(job);
num_slots_idle--;
if (!mali_pp_job_has_unstarted_sub_jobs(job))
{
/*
* All sub jobs have now started for this job, remove this job from the job queue.
* The job will now only be referred to by the slots which are running it.
* The last slot to complete will make sure it is returned to user space.
*/
_mali_osk_list_del(&job->list);
#if MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP
MALI_DEBUG_PRINT(6, ("Mali PP scheduler: Skip scheduling more jobs when MALI_PP_SCHEDULER_FORCE_NO_JOB_OVERLAP is set.\n"));
return;
#endif
}
}
else
{
MALI_DEBUG_PRINT(3, ("Mali PP scheduler: Failed to start PP job\n"));
return;
}
}
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job, mali_bool restart_virtual)
{
u32 num_frame_registers;
u32 relative_address;
u32 start_index;
u32 nr_of_regs;
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
core->counter_src0_used = mali_pp_job_get_perf_counter_src0(job);
core->counter_src1_used = mali_pp_job_get_perf_counter_src1(job);
MALI_DEBUG_ASSERT_POINTER(core);
/* Write frame registers */
num_frame_registers = (_MALI_PRODUCT_ID_MALI200 == mali_kernel_core_get_product_id()) ? MALI_PP_MALI200_NUM_FRAME_REGISTERS : MALI_PP_MALI400_NUM_FRAME_REGISTERS;
/*
* There are two frame registers which are different for each sub job:
* 1. The Renderer List Address Register (MALI200_REG_ADDR_FRAME)
* 2. The FS Stack Address Register (MALI200_REG_ADDR_STACK)
*/
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_FRAME / sizeof(u32)]);
/* For virtual jobs, the stack address shouldn't be broadcast but written individually */
if (!mali_pp_job_is_virtual(job) || restart_virtual)
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_STACK / sizeof(u32)]);
}
/* Write registers between MALI200_REG_ADDR_FRAME and MALI200_REG_ADDR_STACK */
relative_address = MALI200_REG_ADDR_RSW;
start_index = MALI200_REG_ADDR_RSW / sizeof(u32);
nr_of_regs = (MALI200_REG_ADDR_STACK - MALI200_REG_ADDR_RSW) / sizeof(u32);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core,
relative_address, &frame_registers[start_index],
nr_of_regs, &mali_frame_registers_reset_values[start_index]);
/* MALI200_REG_ADDR_STACK_SIZE */
relative_address = MALI200_REG_ADDR_STACK_SIZE;
start_index = MALI200_REG_ADDR_STACK_SIZE / sizeof(u32);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core,
relative_address, frame_registers[start_index],
mali_frame_registers_reset_values[start_index]);
/* Skip 2 reserved registers */
/* Write remaining registers */
relative_address = MALI200_REG_ADDR_ORIGIN_OFFSET_X;
start_index = MALI200_REG_ADDR_ORIGIN_OFFSET_X / sizeof(u32);
nr_of_regs = num_frame_registers - MALI200_REG_ADDR_ORIGIN_OFFSET_X / sizeof(u32);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core,
relative_address, &frame_registers[start_index],
nr_of_regs, &mali_frame_registers_reset_values[start_index]);
/* Write WBx registers */
if (wb0_registers[0]) /* M200_WB0_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (wb1_registers[0]) /* M200_WB1_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (wb2_registers[0]) /* M200_WB2_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
/* Adding barrier to make sure all rester writes are finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
/* Adding barrier to make sure previous rester writes is finished */
_mali_osk_write_mem_barrier();
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job)
{
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, frame_registers, MALI200_NUM_REGS_FRAME);
if (0 != sub_job)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job));
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job));
}
if (wb0_registers[0])
{
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, MALI200_NUM_REGS_WBx);
}
if (wb1_registers[0])
{
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, MALI200_NUM_REGS_WBx);
}
if (wb2_registers[0])
{
mali_hw_core_register_write_array_relaxed(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, MALI200_NUM_REGS_WBx);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
}
else
{
u32 perf_counter_flag = mali_pp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_pp_job_get_perf_counter_src0(job);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_pp_job_get_perf_counter_src1(job);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
_mali_osk_write_mem_barrier();
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
_mali_osk_write_mem_barrier();
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_pp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH, job->frame_builder_id, job->flush_id, 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id), job->pid, job->tid, 0, 0, 0);
#endif
core->running_job = job;
core->running_sub_job = sub_job;
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job)
{
u32 relative_address;
u32 start_index;
u32 nr_of_regs;
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
u32 counter_src0 = mali_pp_job_get_perf_counter_src0(job, sub_job);
u32 counter_src1 = mali_pp_job_get_perf_counter_src1(job, sub_job);
MALI_DEBUG_ASSERT_POINTER(core);
/* Write registers between MALI200_REG_ADDR_FRAME and MALI200_REG_ADDR_STACK */
relative_address = MALI200_REG_ADDR_RSW;
start_index = MALI200_REG_ADDR_RSW / sizeof(u32);
nr_of_regs = (MALI200_REG_ADDR_STACK - MALI200_REG_ADDR_RSW) / sizeof(u32);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core,
relative_address, &frame_registers[start_index],
nr_of_regs, &mali_frame_registers_reset_values[start_index]);
/* MALI200_REG_ADDR_STACK_SIZE */
relative_address = MALI200_REG_ADDR_STACK_SIZE;
start_index = MALI200_REG_ADDR_STACK_SIZE / sizeof(u32);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core,
relative_address, frame_registers[start_index],
mali_frame_registers_reset_values[start_index]);
/* Skip 2 reserved registers */
/* Write remaining registers */
relative_address = MALI200_REG_ADDR_ORIGIN_OFFSET_X;
start_index = MALI200_REG_ADDR_ORIGIN_OFFSET_X / sizeof(u32);
nr_of_regs = MALI_PP_MALI400_NUM_FRAME_REGISTERS - MALI200_REG_ADDR_ORIGIN_OFFSET_X / sizeof(u32);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core,
relative_address, &frame_registers[start_index],
nr_of_regs, &mali_frame_registers_reset_values[start_index]);
/* Write WBx registers */
if (wb0_registers[0]) { /* M200_WB0_REG_SOURCE_SELECT register */
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (wb1_registers[0]) { /* M200_WB1_REG_SOURCE_SELECT register */
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (wb2_registers[0]) { /* M200_WB2_REG_SOURCE_SELECT register */
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, _MALI_PP_MAX_WB_REGISTERS, mali_wb_registers_reset_values);
}
if (MALI_HW_CORE_NO_COUNTER != counter_src0) {
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, counter_src0);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (MALI_HW_CORE_NO_COUNTER != counter_src1) {
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, counter_src1);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
#ifdef CONFIG_MALI400_HEATMAPS_ENABLED
if(job->uargs.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_HEATMAP_ENABLE) {
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERFMON_CONTR, ((job->uargs.tilesx & 0x3FF) << 16) | 1);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERFMON_BASE, job->uargs.heatmap_mem & 0xFFFFFFF8);
}
#endif /* CONFIG_MALI400_HEATMAPS_ENABLED */
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
/* Adding barrier to make sure all rester writes are finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
/* Adding barrier to make sure previous rester writes is finished */
_mali_osk_write_mem_barrier();
}
