static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount()==0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } maliDvfsStatus.currentStep = validatedStep; /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; return MALI_TRUE; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; int err; if (mali_step_lock > -1 && step != mali_step_lock) { step = mali_step_lock; } #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } #ifdef EXYNOS4_ASV_ENABLED #ifndef CONFIG_ABB_CONTROL if (samsung_rev() < EXYNOS4412_REV_2_0) { if (mali_dvfs[step].clock == 160) exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); } #else abb_target(ABB_G3D, mali_dvfs[step].clock*1000); #endif #endif set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[step].clock == 440) err = cpufreq_lock_by_mali(1200); else cpufreq_unlock_by_mali(); #endif return MALI_TRUE; }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; if (mali_clock != 0) return ret; // already initialized mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_dvfs_lock == NULL) return _MALI_OSK_ERR_FAULT; if (mali_clk_set_rate(mali_gpu_clk, GPU_MHZ) == MALI_FALSE) { ret = MALI_FALSE; goto err_clock_get; } MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock)); #ifdef CONFIG_REGULATOR #if USING_MALI_PMM g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d"); #else g3d_regulator = regulator_get(NULL, "vdd_g3d"); #endif if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } regulator_enable(g3d_regulator); MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount())); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); #endif MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n")); MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__)); MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock - normal\n", __FUNCTION__)); mali_clk_put(MALI_FALSE); gpu_power_state = 0; bPoweroff = 1; return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_clock_get: mali_clk_put(MALI_TRUE); return ret; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; int err; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } #ifdef EXYNOS4_ASV_ENABLED if (mali_dvfs[step].clock == 160) exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); #endif set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; /* lock/unlock CPU freq by Mali */ /* if ((mali_dvfs[step].clock == 533) || (mali_dvfs[step].clock == 440)) #if defined(CONFIG_EXYNOS4X12_1800MHZ_SUPPORT) err = cpufreq_lock_by_mali(1800); #elif defined(CONFIG_EXYNOS4X12_1600MHZ_SUPPORT) err = cpufreq_lock_by_mali(1600); #elif defined(CONFIG_EXYNOS4X12_1500MHZ_SUPPORT) err = cpufreq_lock_by_mali(1500); #elif defined(CONFIG_EXYNOS4X12_1400MHZ_SUPPORT) err = cpufreq_lock_by_mali(1400); #else err = cpufreq_lock_by_mali(1200); #endif else cpufreq_unlock_by_mali(); */ return MALI_TRUE; }
void mali_regulator_enable(void) { if (IS_ERR_OR_NULL(g3d_regulator)) { MALI_DEBUG_PRINT(1, ("error on mali_regulator_enable : g3d_regulator is null\n")); return; } regulator_enable(g3d_regulator); bPoweroff = 0; MALI_DEBUG_PRINT(1, ("regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount())); }
void mali_regulator_disable(void) { if( g3d_regulator==NULL ) { MALI_DEBUG_PRINT(1, ("error on mali_regulator_disable : g3d_regulator is null\n")); return; } regulator_disable(g3d_regulator); MALI_DEBUG_PRINT(1, ("regulator_disable -> use cnt: %d \n",mali_regulator_get_usecount())); }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; int err; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[step].clock >= 533) err = cpufreq_lock_by_mali(1200); else if (mali_dvfs[step].clock == 440) err = cpufreq_lock_by_mali(1000); else cpufreq_unlock_by_mali(); #endif return MALI_TRUE; }
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup) { u32 validatedStep=step; #ifdef CONFIG_REGULATOR if (mali_regulator_get_usecount() == 0) { MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n")); return MALI_FALSE; } #endif if (boostup) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); } else { /*change the clock*/ mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq); #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol); #endif } #ifdef EXYNOS4_ASV_ENABLED if (samsung_rev() < EXYNOS4412_REV_2_0) { if (mali_dvfs[step].clock == 160) exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V); } #endif set_mali_dvfs_current_step(validatedStep); /*for future use*/ maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep]; return MALI_TRUE; }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; gpu_power_state = 0; bPoweroff = 1; if (mali_clock != 0) return ret; // already initialized mpll_clock = clk_get(NULL,MPLLCLK_NAME); if (IS_ERR(mpll_clock)) { MALI_PRINT( ("MALI Error : failed to get source mpll clock\n")); ret = MALI_FALSE; goto err_mpll_clk; } mali_parent_clock = clk_get(NULL, GPUMOUT0CLK_NAME); if (IS_ERR(mali_parent_clock)) { MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n")); ret = MALI_FALSE; goto err_gpu_parent_clk; } mali_clock = clk_get(NULL, GPUCLK_NAME); if (IS_ERR(mali_clock)) { MALI_PRINT( ("MALI Error : failed to get source mali clock\n")); ret = MALI_FALSE; goto err_gpu_clk; } clk_set_parent(mali_parent_clock, mpll_clock); clk_set_parent(mali_clock, mali_parent_clock); clk_set_rate(mali_clock, (unsigned int)mali_gpu_clk * GPU_MHZ); MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock)); #ifdef CONFIG_REGULATOR #if USING_MALI_PMM g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d"); #else g3d_regulator = regulator_get(NULL, "vdd_g3d"); #endif if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } regulator_enable(g3d_regulator); MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount())); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); #endif MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n")); MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__)); MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock - normal\n", __FUNCTION__)); clk_put(mali_parent_clock); clk_put(mpll_clock); return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_gpu_clk: MALI_DEBUG_PRINT(3, ("::clk_put:: %s mali_clock\n", __FUNCTION__)); clk_put(mali_clock); mali_clock = 0; err_gpu_parent_clk: MALI_DEBUG_PRINT(3, ("::clk_put:: %s mali_parent_clock\n", __FUNCTION__)); clk_put(mali_parent_clock); mali_parent_clock = 0; err_mpll_clk: MALI_DEBUG_PRINT(3, ("::clk_put:: %s mpll_clock\n", __FUNCTION__)); clk_put(mpll_clock); mpll_clock = 0; return ret; }