/*
* XLP8XX/4XX/3XX/2XX:
* The MSI-X interrupt handling is different from MSI, there are 32 MSI-X
* interrupts generated by the PIC and each of these correspond to a MSI-X
* vector (0-31) that can be assigned.
*
* We divide the MSI-X vectors to 8 per link and do a per-link allocation
*
* XLP9XX:
* 32 MSI-X vectors are available per link, and the interrupts are not routed
* thru the PIC. PIC ack not needed.
*
* Enable and disable done using standard MSI functions.
*/
static void xlp_msix_mask_ack(struct irq_data *d)
{
struct xlp_msi_data *md;
int link, msixvec;
uint32_t status_reg, bit;
msixvec = nlm_irq_msixvec(d->irq);
link = nlm_irq_msixlink(msixvec);
mask_msi_irq(d);
md = irq_data_get_irq_handler_data(d);
/* Ack MSI on bridge */
if (cpu_is_xlp9xx()) {
status_reg = PCIE_9XX_MSIX_STATUSX(link);
bit = msixvec % XLP_MSIXVEC_PER_LINK;
} else {
status_reg = PCIE_MSIX_STATUS;
bit = msixvec;
}
nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
/* Ack at eirr and PIC */
ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
if (!cpu_is_xlp9xx())
nlm_pic_ack(md->node->picbase,
PIC_IRT_PCIE_MSIX_INDEX(msixvec));
}
static void imx_msi_irq_mask(struct irq_data *d)
{
imx_pcie_mask_irq(d->irq - IRQ_IMX_MSI_0, 1);
return mask_msi_irq(d);
}
static void imx_msi_irq_disable(struct irq_data *d)
{
imx_pcie_enable_irq(d->irq - IRQ_IMX_MSI_0, 0);
return mask_msi_irq(d);
}
