irqreturn_t mdp4_irq(struct msm_kms *kms) { struct mdp_kms *mdp_kms = to_mdp_kms(kms); struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); struct drm_device *dev = mdp4_kms->dev; struct msm_drm_private *priv = dev->dev_private; unsigned int id; uint32_t status, enable; enable = mdp4_read(mdp4_kms, REG_MDP4_INTR_ENABLE); status = mdp4_read(mdp4_kms, REG_MDP4_INTR_STATUS) & enable; mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, status); VERB("status=%08x", status); mdp_dispatch_irqs(mdp_kms, status); for (id = 0; id < priv->num_crtcs; id++) if (status & mdp4_crtc_vblank(priv->crtcs[id])) drm_handle_vblank(dev, id); return IRQ_HANDLED; }
/* set interface for routing crtc->encoder: */ void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf) { struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); struct mdp4_kms *mdp4_kms = get_kms(crtc); uint32_t intf_sel; intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL); switch (mdp4_crtc->dma) { case DMA_P: intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK; intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf); break; case DMA_S: intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK; intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf); break; case DMA_E: intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK; intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf); break; } if (intf == INTF_DSI_VIDEO) { intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD; intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO; mdp4_crtc->mixer = 0; } else if (intf == INTF_DSI_CMD) { intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO; intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD; mdp4_crtc->mixer = 0; } else if (intf == INTF_LCDC_DTV){ mdp4_crtc->mixer = 1; } blend_setup(crtc); DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel); mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); }
static int mdp4_hw_init(struct msm_kms *kms) { struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); struct drm_device *dev = mdp4_kms->dev; uint32_t version, major, minor, dmap_cfg, vg_cfg; unsigned long clk; int ret = 0; pm_runtime_get_sync(dev->dev); mdp4_enable(mdp4_kms); version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); mdp4_disable(mdp4_kms); major = FIELD(version, MDP4_VERSION_MAJOR); minor = FIELD(version, MDP4_VERSION_MINOR); DBG("found MDP4 version v%d.%d", major, minor); if (major != 4) { dev_err(dev->dev, "unexpected MDP version: v%d.%d\n", major, minor); ret = -ENXIO; goto out; } mdp4_kms->rev = minor; if (mdp4_kms->rev > 1) { mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); } mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); /* max read pending cmd config, 3 pending requests: */ mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); clk = clk_get_rate(mdp4_kms->clk); if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ } else { dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ } DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); if (mdp4_kms->rev >= 2) mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); /* disable CSC matrix / YUV by default: */ mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); if (mdp4_kms->rev > 1) mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); dev->mode_config.allow_fb_modifiers = true; out: pm_runtime_put_sync(dev->dev); return ret; }