void MstarSysInit(void)
{
uint u32Tmp;
extern MS_BOOL MDrv_MIU_SetIOMapBase(void);
extern MS_BOOL MDrv_SEM_Init(void);
MsOS_Init();
MDrv_MMIO_Init();
MDrv_MMIO_GetBASE((MS_U32 *)&MS_RIU_MAP, (MS_U32 *)&u32Tmp, MS_MODULE_PM);
MDrv_SEM_Init();
MDrv_MIU_SetIOMapBase();
MsOS_CPU_EnableInterrupt();
#if (ENABLE_MODULE_ENV_IN_SERIAL==1)
puts ("SPI: ");
{
extern int spi_init (void);
spi_init(); /* go init the SPI */
}
#if (CONFIG_MSTAR_BD_MST028B_10AFX_EAGLE||CONFIG_MSTAR_BD_MST038B_10AHT_EAGLE)
MDrv_SERFLASH_SetWPInfo(TRUE);
#else
ms_Flash_SetHWWP_CB pCB = msFlash_ActiveFlash_Set_HW_WP;
MDrv_SERFLASH_SetFlashWPCallBack(pCB);
#endif
#else
#if(ENABLE_BOOTING_FROM_EXT_EMMC_WITH_CPU==0)
MDrv_SERFLASH_Init();
#endif
#endif
mdrv_gpio_init();
run_command("init_raw_io" , 0);
run_command("config_raw_io" , 0);
}
void MstarSysInit(void)
{
uint u32Tmp;
/*set up Mstar IRQ handler*/
extern void mhal_fiq_merge(void);
extern void MAsm_CPU_TimerStart(void);
extern void dcache_init(void);
extern void l2_cache_init(void);
mhal_fiq_merge();
MsOS_Init();
#ifdef CONFIG_SYS_DCACHE
dcache_init();
#endif
#ifndef CONFIG_L2_OFF
l2_cache_init();
#endif
#if defined(CONFIG_TIMER_TEST)
MDrv_Timer_ISR_Register();
#endif
MsOS_CPU_EnableInterrupt();
MAsm_CPU_TimerStart();
MDrv_MMIO_Init();
MDrv_MMIO_GetBASE((MS_U32 *)&MS_RIU_MAP, (MS_U32 *)&u32Tmp, MS_MODULE_PM);
#if (ENABLE_MODULE_ENV_IN_SERIAL==1)
puts ("SPI: ");
{
extern int spi_init (void);
spi_init(); /* go init the SPI */
}
#if (CONFIG_MSTAR_BD_MST028B_10AFX_EAGLE||CONFIG_MSTAR_BD_MST038B_10AHT_EAGLE)
MDrv_SERFLASH_SetWPInfo(TRUE);
#else
ms_Flash_SetHWWP_CB pCB = msFlash_ActiveFlash_Set_HW_WP;
MDrv_SERFLASH_SetFlashWPCallBack(pCB);
FlashSetHWWPCB = FlashSetHWWPCB;
McuChipSelectCB = McuChipSelectCB;
#endif
#else
#if(ENABLE_BOOTING_FROM_EXT_EMMC_WITH_CPU==0)
MDrv_SERFLASH_Init();
#endif
#endif
mdrv_gpio_init();
MDrv_BDMA_Init(MIU_INTERVAL);
run_command("init_raw_io" , 0);
run_command("config_raw_io" , 0);
}
void iic_init()
{
//global init
MDrv_SYS_GlobalInit();
//gpio init
mdrv_gpio_init();
//software i2c init
SWI2C_BusCfg swBusCfg = {SCL_GPIO_PORT,
SDA_GPIO_PORT,
75};
MApi_SWI2C_Init(&swBusCfg, 1);
mdrv_gpio_set_input(KEY_FLAG_SAR_PORT);
}
int nmi_tuner_os_chip_enable(void)
{
#if 0
//hardware reset sar3 high
extern void Enable_SAR_GPIO(MS_U8 u8SarNo,MS_BOOL bEnable);
extern void mdrv_gpio_set_high(int gpio);
extern void mdrv_gpio_init(void);
mdrv_gpio_init();
Enable_SAR_GPIO(3,SAR3_GPIO_ENABLE);
mdrv_gpio_set_high(20);
MsOS_DelayTask(100);
#endif
return TRUE;
}
void drvTAS5707_SW_Init(void)
{
#if (MS_BOARD_TYPE_SEL == BD_MST119A_D01A_S_HISENSE)
U8 * Pstr = NULL;
U8 DataLength = 0;
U8 g_ucTas5707RegAddr = 0;
U8 AmpInitTbl[] =
{
//DataLength Address DataN DataN+1...
// I2C Configuration file for TAS5700x
1, 0x1B, 0x00,
// Biquads
4, 0x50, 0x0F, 0x70, 0x80, 0x00,
4, 0x20, 0x00, 0x89, 0x77, 0x72,
4, 0x25, 0x01, 0x13, 0x20, 0x45,
20, 0x29, 0x00, 0x7E, 0x82, 0x70, 0x0F, 0x81, 0x7D, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7D, 0x04, 0xE0, 0x00, 0x00, 0x00, 0x00,
20, 0x2A, 0x00, 0x7E, 0x39, 0xA9, 0x0F, 0x05, 0x88, 0xEA, 0x00, 0x7C, 0x95, 0x6B, 0x00, 0xFA, 0x77, 0x16, 0x0F, 0x85, 0x30, 0xEB,
20, 0x2B, 0x00, 0x92, 0x0D, 0x64, 0x0F, 0x51, 0xAE, 0x7F, 0x00, 0x49, 0xAB, 0xD2, 0x00, 0xAE, 0x51, 0x81, 0x0F, 0xA4, 0x46, 0xC9,
20, 0x2C, 0x00, 0xBA, 0x7D, 0x1C, 0x0F, 0xB2, 0xBC, 0x64, 0x00, 0x0F, 0x69, 0x81, 0x00, 0x4D, 0x43, 0x9C, 0x0F, 0xB6, 0x19, 0x63,
20, 0x2D, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20, 0x2E, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20, 0x30, 0x00, 0x7E, 0x82, 0x70, 0x0F, 0x81, 0x7D, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7D, 0x04, 0xE0, 0x00, 0x00, 0x00, 0x00,
20, 0x31, 0x00, 0x7E, 0x39, 0xA9, 0x0F, 0x05, 0x88, 0xEA, 0x00, 0x7C, 0x95, 0x6B, 0x00, 0xFA, 0x77, 0x16, 0x0F, 0x85, 0x30, 0xEB,
20, 0x32, 0x00, 0x92, 0x0D, 0x64, 0x0F, 0x51, 0xAE, 0x7F, 0x00, 0x49, 0xAB, 0xD2, 0x00, 0xAE, 0x51, 0x81, 0x0F, 0xA4, 0x46, 0xC9,
20, 0x33, 0x00, 0xBA, 0x7D, 0x1C, 0x0F, 0xB2, 0xBC, 0x64, 0x00, 0x0F, 0x69, 0x81, 0x00, 0x4D, 0x43, 0x9C, 0x0F, 0xB6, 0x19, 0x63,
20, 0x34, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20, 0x35, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20, 0x36, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// DRCs
8, 0x3A, 0x00, 0x00, 0x06, 0xD3, 0x00, 0x7F, 0xF9, 0x2B,
8, 0x3B, 0x00, 0x02, 0xA3, 0x9A, 0x00, 0x7D, 0x2F, 0xD2,
8, 0x3C, 0x00, 0x00, 0x06, 0xd3, 0x00, 0x7f, 0xf9, 0x2B,
4, 0x40, 0xFD, 0x97, 0x73, 0x3D,
4, 0x41, 0x03, 0x81, 0x47, 0xAF,
4, 0x42, 0x00, 0x08, 0x42, 0x10,
4, 0x46, 0x00, 0x00, 0x00, 0x01,
1, 0x07, 0x10,
1, 0x05, 0x00,
1, 0x08, 0x30, //Channel 1 Volume
1, 0x09, 0x30, //Channel 2 Volume
1, 0x06, 0x00, //Soft Mute Register (mute off)
1, 0x03, 0xA0, //System Control Register 1(opt.)
1, 0x04, 0x05, //Serial Data Interface Register
1, 0x0E, 0x91, //Micro Register(opt.)
1, 0x10, 0x02, //Modulation Limit(opt.)
1, 0x1A, 0x0A, //Split Capacitor Charge Period(opt.)
1, 0x1C, 0x02, //Back-end Error Register(opt.)
1, 0x11, 0xB8, //Inter-Channel Delay Channel 1
1, 0x12, 0x60, //Inter-Channel Delay Channel 2
1, 0x13, 0xA0, //Inter-Channel Delay Channel 3
1, 0x14, 0x48, //Inter-Channel Delay Channel 4
0x00,
};
printf("********Amplifier_Init\n");
//===========================================
mdrv_gpio_init();
mdrv_gpio_set_low(BALL_W20);
udelay(1000);
mdrv_gpio_set_low(BALL_Y20);
udelay(1000);
mdrv_gpio_set_high(BALL_W20);
udelay(20*1000);
Pstr = AmpInitTbl;
do
{
DataLength = *Pstr;
if (DataLength > 20)
{
printf("5707 set command error!!\n");
break;
}
g_ucTas5707RegAddr = *(++Pstr);
Pstr++;
if (MApi_SWI2C_WriteBytes(((U16)((E_I2C_BUS_SYS << 8) | 0x36)), 1,&g_ucTas5707RegAddr, DataLength, Pstr) == FALSE)
printf("5707write fail = %d\n", g_ucTas5707RegAddr);
if (g_ucTas5707RegAddr == 0x1B)
{
udelay(50*1000);
}
else// if (i<=5)
{
udelay(1*1000);
}
Pstr = Pstr + DataLength;
} while (*Pstr != 0);
#elif (ENABLE_MSTAR_TITANIA_BD_MSTCUS23_6A801_A3)
{
U8 * Pstr = NULL;
U8 DataLength = 0;
U8 g_ucTas5707RegAddr = 0;
U8 AmpInitTbl[] =
{
//DataLength Address DataN DataN+1...
// I2C Configuration file for TAS5700x
//i2c writes
0x01, 0x1B, 0x00,//Os`cillator Trim(place a 50ms delay after writing this register)
//(Below) DRC energy time(100ms)
0x08, 0x3A, 0x00, 0x00, 0x06, 0xD3, 0x00, 0x7F, 0xF9, 0x2B,
//(Below) DRC attack time(1ms)
0x08, 0x3B, 0x00, 0x02, 0xA3, 0x9A, 0x00, 0x7D, 0x2F, 0xD2,
//(Below) DRC decay time(100ms)
0x08, 0x3C, 0x00, 0x00, 0x06, 0xD3, 0x00, 0x7F, 0xF9, 0x2B,
0x04, 0x40, 0xFD, 0xAC, 0xB5, 0xE3,//0xFD, 0x9F, 0xF4, 0x4C,
//(Below) DRC compression ratio(100)
0x04, 0x41, 0x03, 0x81, 0x47, 0xAF,
//(Below) DRC offset(0)
0x04, 0x42, 0x00, 0x08, 0x42, 0x10,
//(Below) DRC control(DRC enable)
0x04, 0x46, 0x00, 0x00, 0x00, 0x01,
//(Below) Bank switch control (no automatic bank switching)
0x04, 0x50, 0x0F, 0x70, 0x80, 0x00,
0x04, 0x20, 0x00, 0x98, 0x77, 0x72, //
//0x04, 0x20, 0x00, 0x89, 0x77, 0x72, //change vol balance lmy 110714
//(Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay,R:A+,B-,L:C+,D-)
0x04, 0x25, 0x01, 0x02, 0x13, 0x45,
0x01, 0x07, 0x15,//0x16, //Master Volume Register (0xFF = Mute,16dB)
0x01, 0x08, 0x30, //Channel 1 Volume
0x01, 0x09, 0x30, //Channel 2 Volume
0x01, 0x06, 0x00, //Soft Mute Register (mute off)
0x01, 0x03, 0xA0, //System Control Register 1(opt.)
0x01, 0x04, 0x05, //Serial Data Interface Register
0x01, 0x05, 0x00, //System Control Register 2(exit hard mute)
0x01, 0x0E, 0x91, //Micro Register(opt.)
0x01, 0x10, 0x02, //Modulation Limit(opt.)
0x01, 0x1A, 0x0A, //Split Capacitor Charge Period(opt.)
0x01, 0x1C, 0x02, //Back-end Error Register(opt.)
0x01, 0x11, 0xB8, //Inter-Channel Delay Channel 1
0x01, 0x12, 0x60, //Inter-Channel Delay Channel 2
0x01, 0x13, 0xA0, //Inter-Channel Delay Channel 3
0x01, 0x14, 0x48, //Inter-Channel Delay Channel 4
0x00
};
U8 Amp5707A_InitTbl[] =
{
//i2c writes
0x01, 0x1B, 0x00,//Os`cillator Trim(place a 50ms delay after writing this register)
//(Below) DRC energy time(100ms)
0x08, 0x3A, 0x00, 0x00, 0x06, 0xD3, 0x00, 0x7F, 0xF9, 0x2B,
//(Below) DRC attack time(1ms)
0x08, 0x3B, 0x00, 0x02, 0xA3, 0x9A, 0x00, 0x7D, 0x2F, 0xD2,
//(Below) DRC decay time(100ms)
0x08, 0x3C, 0x00, 0x00, 0x06, 0xD3, 0x00, 0x7F, 0xF9, 0x2B,
//(Below) DRC thresh
0x04, 0x40, 0xFD, 0x9F, 0xF4, 0x4C, //same as 5707
//(Below) DRC compression ratio(100)
0x04, 0x41, 0x03, 0x81, 0x47, 0xAF,
//(Below) DRC offset(0)
0x04, 0x42, 0x00, 0x08, 0x42, 0x10,
//(Below) DRC control(DRC enable)
0x04, 0x46, 0x00, 0x00, 0x00, 0x01,
0x14, 0x29, 0x00, 0x00, 0x40, 0x8D, 0x00, 0x00, 0x81, 0x1B, 0x00, 0x00, 0x40, 0x8D, 0x00, 0xEF, 0x6E, 0x9F, 0x0F, 0x8F, 0x8F, 0x29,//45Hz
0x14, 0x30, 0x00, 0x00, 0x40, 0x8D, 0x00, 0x00, 0x81, 0x1B, 0x00, 0x00, 0x40, 0x8D, 0x00, 0xEF, 0x6E, 0x9F, 0x0F, 0x8F, 0x8F, 0x29,//45Hz
0x14, 0x2A, 0x00, 0x82, 0x80, 0x27, 0x0F, 0x03, 0x5D, 0x04, 0x00, 0x7A, 0x31, 0x04, 0x00, 0xFC, 0xA2, 0xFC, 0x0F, 0x83, 0x4E, 0xD4,//700MHz
0x14, 0x31, 0x00, 0x82, 0x80, 0x27, 0x0F, 0x03, 0x5D, 0x04, 0x00, 0x7A, 0x31, 0x04, 0x00, 0xFC, 0xA2, 0xFC, 0x0F, 0x83, 0x4E, 0xD4,//700MHz
0x14, 0x2B, 0x00, 0x7F, 0x2C, 0x58, 0x0F, 0x01, 0xA7, 0x50, 0x00, 0x7F, 0x2C, 0x58, 0x00, 0xFE, 0x57, 0x52, 0x0F, 0x81, 0xA5, 0xF2,//45Hz
0x14, 0x32, 0x00, 0x7F, 0x2C, 0x58, 0x0F, 0x01, 0xA7, 0x50, 0x00, 0x7F, 0x2C, 0x58, 0x00, 0xFE, 0x57, 0x52, 0x0F, 0x81, 0xA5, 0xF2,//45Hz
0x14, 0x2C, 0x00, 0x75, 0x76, 0x29, 0x0F, 0x19, 0x61, 0xFB, 0x00, 0x72, 0x6D, 0x0E, 0x00, 0xE6, 0x9E, 0x05, 0x0F, 0x98, 0x1C, 0xC8,//700MHz
0x14, 0x33, 0x00, 0x75, 0x76, 0x29, 0x0F, 0x19, 0x61, 0xFB, 0x00, 0x72, 0x6D, 0x0E, 0x00, 0xE6, 0x9E, 0x05, 0x0F, 0x98, 0x1C, 0xC8,//700MHz
0x14, 0x2D, 0x00, 0x80, 0x6A, 0x60, 0x0F, 0x00, 0xDB, 0x5E, 0x00, 0x7E, 0xBF, 0xDB, 0x00, 0xFF, 0x24, 0xA2, 0x0F, 0x80, 0xD5, 0xC5,//700MHz
0x14, 0x34, 0x00, 0x80, 0x6A, 0x60, 0x0F, 0x00, 0xDB, 0x5E, 0x00, 0x7E, 0xBF, 0xDB, 0x00, 0xFF, 0x24, 0xA2, 0x0F, 0x80, 0xD5, 0xC5,//700MHz
//(Below) ch1 Biquad1 Coeff(low pass butterworth 2 200Hz)
// 0x14, 0x2B, 0x00, 0x81, 0x49, 0x88, 0x0F, 0x03, 0x92, 0xB6, 0x00, 0x7B, 0x67, 0xA3, 0x00, 0xFC, 0x6D, 0x4A, 0x0F, 0x83, 0x4E, 0xD4,
//00, 0x80, 0x52, 0x7D, 0x0F, 0x02, 0xC1, 0x44, 0x00, 0x7D, 0x30, 0x59, 0x00, 0xFD, 0x3E, 0xBC, 0x0F, 0x82, 0x7D, 0x2A,
//00,0x80,0x52,0x7D,0x0F,0x02,0xC1,0x44,0x00,0x7D,0x30,0x59,0x00,0xFD,0x3E,0xBC,0x0F,0x82,0x7D,0x2A,
// 00, 0x00, 0x05, 0x83, 0x00, 0x00, 0x0B, 0x06, 0x00, 0x00, 0x05, 0x83, 0x00, 0xFB, 0x42, 0xC1, 0x0F, 0x84, 0xA7, 0x33,
//(Below) ch1 Biquad2 Coeff(high pass butterworth 2 45Hz)
//0x14, 0x2C, 0x00, 0x7F, 0x77, 0xC7, 0x0F, 0x01, 0x10, 0x72, 0x00, 0x7F, 0x77, 0xC7, 0x00, 0xFE, 0xEE, 0xFD, 0x0F, 0x81, 0x0F, 0xE1,
//(Below) ch2 Biquad1 Coeff(low pass butterworth 2 200Hz)
//0x14, 0x32, 0x00, 0x81, 0x49, 0x88, 0x0F, 0x03, 0x92, 0xB6, 0x00, 0x7B, 0x67, 0xA3, 0x00, 0xFC, 0x6D, 0x4A, 0x0F, 0x83, 0x4E, 0xD4,
//00, 0x80, 0x52, 0x7D, 0x0F, 0x02, 0xC1, 0x44, 0x00, 0x7D, 0x30, 0x59, 0x00, 0xFD, 0x3E, 0xBC, 0x0F, 0x82, 0x7D, 0x2A,//350hZ
//00, 0x00, 0x05, 0x83, 0x00, 0x00, 0x0B, 0x06, 0x00, 0x00, 0x05, 0x83, 0x00, 0xFB, 0x42, 0xC1, 0x0F, 0x84, 0xA7, 0x33,
//(Below) ch2 Biquad2 Coeff(high pass butterworth 2 45Hz)
//0x14, 0x33, 0x00, 0x7F, 0x77, 0xC7, 0x0F, 0x01, 0x10, 0x72, 0x00, 0x7F, 0x77, 0xC7, 0x00, 0xFE, 0xEE, 0xFD, 0x0F, 0x81, 0x0F, 0xE1,
//(Below) Bank switch control (no automatic bank switching)
0x04, 0x50, 0x0F, 0x70, 0x80, 0x00,
0x04, 0x20, 0x00, 0x80, 0x77, 0x72,
//0x04, 0x20, 0x00, 0x89, 0x77, 0x72,
//(Below) PWM Output MUX Register (Note: Writes to this register affect Inter-Channel Delay,R:A+,B-,L:C+,D-)
0x04, 0x25, 0x01, 0x20, 0x31, 0x45,
0x01, 0x07, 0x16, //Master Volume Register (0xFF = Mute,16dB) //same as 5707
0x01, 0x08, 0x30, //Channel 1 Volume
0x01, 0x09, 0x30, //Channel 2 Volume
0x01, 0x06, 0x00, //Soft Mute Register (mute off)
0x01, 0x03, 0xA0, //System Control Register 1(opt.)
0x01, 0x04, 0x05, //Serial Data Interface Register
0x01, 0x05, 0x00, //System Control Register 2(exit hard mute)
0x01, 0x0E, 0x91, //Micro Register(opt.)
0x01, 0x10, 0x02, //Modulation Limit(opt.)
0x01, 0x1A, 0x0A, //Split Capacitor Charge Period(opt.)
0x01, 0x1C, 0x02, //Back-end Error Register(opt.)
0x01, 0x11, 0xB8, //Inter-Channel Delay Channel 1
0x01, 0x12, 0x60, //Inter-Channel Delay Channel 2
0x01, 0x13, 0xA0, //Inter-Channel Delay Channel 3
0x01, 0x14, 0x48, //Inter-Channel Delay Channel 4
0x00
};
printf("********Amplifier_Init\n");
//===========================================
mdrv_gpio_init();
Audio_Amplifier_OFF();
msAPI_Timer_Delayms(1);
Audio_Amplifier_ON();
msAPI_Timer_Delayms(20);//must added
Pstr = AmpInitTbl;
do
{
DataLength = *Pstr;
if (DataLength > 20)
{
printf("5707 set command error!!\n");
break;
}
g_ucTas5707RegAddr = *(++Pstr);
Pstr++;
if (MApi_SWI2C_WriteBytes(((U16)((E_I2C_BUS_SYS << 8) | 0x36)), 1,&g_ucTas5707RegAddr, DataLength, Pstr) == FALSE)
printf("5707write fail = 0x%x\n", g_ucTas5707RegAddr);
if (g_ucTas5707RegAddr == 0x1B)
{
msAPI_Timer_Delayms(50);
}
else// if (i<=5)
{
msAPI_Timer_Delayms(1);
}
Pstr = Pstr + DataLength;
} while (*Pstr != 0);
Pstr = Amp5707A_InitTbl;
do
{
DataLength = *Pstr;
if (DataLength > 20)
{
printf("5707A set command error!!\n");
break;
}
g_ucTas5707RegAddr = *(++Pstr);
Pstr++;
if (MApi_SWI2C_WriteBytes(((U16)((E_I2C_BUS_SYS << 8) | 0x3A)), 1,&g_ucTas5707RegAddr, DataLength, Pstr) == FALSE)
printf("5707Awrite fail = %d\n", g_ucTas5707RegAddr);
if (g_ucTas5707RegAddr == 0x1B)
{
msAPI_Timer_Delayms(50);
}
else// if (i<=5)
{
msAPI_Timer_Delayms(1);
}
Pstr = Pstr + DataLength;
} while (*Pstr != 0);
}
#else
drvTAS5707_Shutdown();
drvTAS5707_HWInit();
msAPI_Timer_Delayms(50);
drvTAS5707_RegInit();
#endif
}
