int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
int ret = NO_ERROR;
struct lcdc_panel_info *lcdc = NULL;
uint32_t mdss_mdp_intf_off = 0;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
mdss_mdp_intf_off = mdss_mdp_intf_offset();
mdp_clk_gating_ctrl();
writel(0x0100, MDP_DISP_INTF_SEL);
mdss_vbif_setup();
mdss_smp_setup(pinfo);
mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
mdss_layer_mixer_setup(fb, pinfo);
writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
writel(0x20020, MDP_CTL_0_BASE + CTL_TOP);
return ret;
}
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
{
uint32_t left_pipe, right_pipe;
dprintf(SPEW, "ENTER: %s\n", __func__);
mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset());
pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB;
mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
mdp_clk_gating_ctrl();
mdss_vbif_setup();
mdss_smp_setup(pinfo, left_pipe, right_pipe);
mdss_qos_remapper_setup();
mdss_source_pipe_config(fb, pinfo, left_pipe);
if (pinfo->lcdc.dual_pipe)
mdss_source_pipe_config(fb, pinfo, right_pipe);
mdss_layer_mixer_setup(fb, pinfo);
if (pinfo->lcdc.dual_pipe)
writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP);
else
writel(0x40, MDP_CTL_0_BASE + CTL_TOP);
writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL);
writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
return 0;
}
int mdp_dsi_video_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
uint32_t mdss_mdp_rev = readl(MDP_HW_REV);
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
ctl0_reg_val = 0x22048;
ctl1_reg_val = 0x24090;
break;
case MDSS_MDP_PIPE_TYPE_DMA:
ctl0_reg_val = 0x22840;
ctl1_reg_val = 0x25080;
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
ctl0_reg_val = 0x22041;
ctl1_reg_val = 0x24082;
break;
}
/* For 8916/8939, MDP INTF registers are double buffered */
if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_108)) {
ctl0_reg_val |= BIT(30);
ctl1_reg_val |= BIT(31);
}
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}
int mdp_dsi_video_on(void)
{
int ret = NO_ERROR;
writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x32090, MDP_CTL_1_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return ret;
}
int mdp_edp_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}
void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
uint32_t intf_base)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
uint32_t mdss_mdp_intf_off;
uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
if (pinfo == NULL)
return;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return;
/*
* MDP programmable fetch is for MDP with rev >= 1.05.
* Programmable fetch is not needed if vertical back porch
* is >= 9.
*/
if (mdp_hw_rev < MDSS_MDP_HW_REV_105 ||
lcdc->v_back_porch >= MDP_MIN_FETCH)
return;
mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display)
adjust_xres /= 2;
/*
* Fetch should always be outside the active lines. If the fetching
* is programmed within active region, hardware behavior is unknown.
*/
v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres +
lcdc->v_front_porch;
h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres +
lcdc->h_front_porch;
vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres;
fetch_lines = v_total - vfp_start;
/*
* In some cases, vertical front porch is too high. In such cases limit
* the mdp fetch lines as the last 12 lines of vertical front porch.
*/
if (fetch_lines > MDSS_MDP_MAX_FETCH)
fetch_lines = MDSS_MDP_MAX_FETCH;
fetch_start = (v_total - fetch_lines) * h_total + 1;
writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off);
writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off);
}
static void mdp_set_intf_base(struct msm_panel_info *pinfo,
uint32_t *intf_sel, uint32_t *sintf_sel,
uint32_t *intf_base, uint32_t *sintf_base)
{
if (pinfo->dest == DISPLAY_2) {
*intf_sel = BIT(16);
*sintf_sel = BIT(8);
*intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
*sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
} else {
*intf_sel = BIT(8);
*sintf_sel = BIT(16);
*intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
*sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
}
dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__,
(pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1",
(pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2");
}
int mdp_dsi_video_off()
{
if(!target_cont_splash_screen())
{
writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
mdss_mdp_intf_offset());
mdelay(60);
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
writel(0xFF777713, MDP_INTR_CLEAR);
}
writel(0x00000000, MDP_INTR_EN);
return NO_ERROR;
}
int mdp_dsi_video_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
uint32_t timing_engine_en;
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
if (pinfo->lcdc.dual_pipe && !pinfo->lcdc.dst_split)
writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
if (pinfo->dest == DISPLAY_1)
timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
else
timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
writel(0x01, timing_engine_en + mdss_mdp_intf_offset());
return NO_ERROR;
}
int mdp_edp_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val;
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
ctl0_reg_val = 0x22048;
break;
case MDSS_MDP_PIPE_TYPE_DMA:
ctl0_reg_val = 0x22840;
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
ctl0_reg_val = 0x22041;
break;
}
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}
int mdp_dsi_video_off(struct msm_panel_info *pinfo)
{
uint32_t timing_engine_en;
if (pinfo->dest == DISPLAY_1)
timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
else
timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
if(!target_cont_splash_screen())
{
writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset());
mdelay(60);
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
writel(0xFF777713, MDP_INTR_CLEAR);
}
writel(0x00000000, MDP_INTR_EN);
return NO_ERROR;
}
void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
if (intf_base == MDP_INTF_1_BASE) {
writel(BIT(8), MDP_TG_SINK);
writel(0x0, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
}
mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
hsync_period = lcdc->h_pulse_width +
lcdc->h_back_porch +
adjust_xres + lcdc->xres_pad + lcdc->h_front_porch;
vsync_period = (lcdc->v_pulse_width +
lcdc->v_back_porch +
pinfo->yres + lcdc->yres_pad +
lcdc->v_front_porch);
hsync_start_x =
lcdc->h_pulse_width +
lcdc->h_back_porch;
hsync_end_x =
hsync_period - lcdc->h_front_porch - 1;
display_vstart = (lcdc->v_pulse_width +
lcdc->v_back_porch)
* hsync_period + lcdc->hsync_skew;
display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
+lcdc->hsync_skew - 1;
if (intf_base == MDP_INTF_0_BASE) { /* eDP */
display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
display_vend -= lcdc->h_front_porch;
}
hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
writel(lcdc->v_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off);
writel(display_vstart, MDP_DISPLAY_V_START_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
writel(display_vend, MDP_DISPLAY_V_END_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
if (intf_base == MDP_INTF_0_BASE) /* eDP */
writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
else
writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
}
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
uint32_t intf_sel = BIT(8);
int ret = NO_ERROR;
uint32_t left_pipe, right_pipe;
struct lcdc_panel_info *lcdc = NULL;
uint32_t mdss_mdp_intf_off = 0;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
if (pinfo->lcdc.split_display) {
writel(0x102, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x2, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
mdss_mdp_intf_off = mdss_mdp_intf_offset();
mdp_clk_gating_ctrl();
if (pinfo->mipi.dual_dsi)
intf_sel |= BIT(16); /* INTF 2 enable */
writel(intf_sel, MDP_DISP_INTF_SEL);
switch (pinfo->pipe_type) {
case MDSS_MDP_PIPE_TYPE_RGB:
left_pipe = MDP_VP_0_RGB_0_BASE;
right_pipe = MDP_VP_0_RGB_1_BASE;
break;
case MDSS_MDP_PIPE_TYPE_DMA:
left_pipe = MDP_VP_0_DMA_0_BASE;
right_pipe = MDP_VP_0_DMA_1_BASE;
break;
case MDSS_MDP_PIPE_TYPE_VIG:
default:
left_pipe = MDP_VP_0_VIG_0_BASE;
right_pipe = MDP_VP_0_VIG_1_BASE;
break;
}
mdss_vbif_setup();
mdss_smp_setup(pinfo, left_pipe, right_pipe);
mdss_qos_remapper_setup();
mdss_source_pipe_config(fb, pinfo, left_pipe);
if (pinfo->lcdc.dual_pipe)
mdss_source_pipe_config(fb, pinfo, right_pipe);
mdss_layer_mixer_setup(fb, pinfo);
writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
writel(0x21f20, MDP_CTL_0_BASE + CTL_TOP);
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
writel(0x21F30, MDP_CTL_1_BASE + CTL_TOP);
}
return ret;
}
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
uint32_t intf_sel = BIT(8);
uint32_t reg;
int ret = NO_ERROR;
uint32_t left_pipe, right_pipe;
struct lcdc_panel_info *lcdc = NULL;
uint32_t mdss_mdp_intf_off = 0;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
if (pinfo->lcdc.split_display) {
reg = BIT(1); /* Command mode */
if (pinfo->lcdc.pipe_swap)
reg |= BIT(4); /* Use intf2 as trigger */
else
reg |= BIT(8); /* Use intf1 as trigger */
writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
mdss_mdp_intf_off = mdss_mdp_intf_offset();
mdp_clk_gating_ctrl();
if (pinfo->mipi.dual_dsi)
intf_sel |= BIT(16); /* INTF 2 enable */
writel(intf_sel, MDP_DISP_INTF_SEL);
mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe);
mdss_vbif_setup();
mdss_smp_setup(pinfo, left_pipe, right_pipe);
mdss_qos_remapper_setup();
mdss_vbif_qos_remapper_setup(pinfo);
mdss_source_pipe_config(fb, pinfo, left_pipe);
if (pinfo->lcdc.dual_pipe)
mdss_source_pipe_config(fb, pinfo, right_pipe);
mdss_layer_mixer_setup(fb, pinfo);
writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
if (pinfo->fbc.enabled)
mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
writel(reg, MDP_CTL_1_BASE + CTL_TOP);
}
return ret;
}
int mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
struct intf_timing_params itp = {0};
if (pinfo == NULL)
return ERR_INVALID_ARGS;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return ERR_INVALID_ARGS;
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
if (intf_base == MDP_INTF_1_BASE) {
writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
}
if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) {
writel(BIT(16), MDP_REG_PPB0_CONFIG);
writel(BIT(5), MDP_REG_PPB0_CNTL);
}
if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
pinfo->fbc.comp_ratio = 1;
itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
itp.yres = pinfo->yres;
itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
itp.h_back_porch = pinfo->lcdc.h_back_porch;
itp.h_front_porch = pinfo->lcdc.h_front_porch;
itp.v_back_porch = pinfo->lcdc.v_back_porch;
itp.v_front_porch = pinfo->lcdc.v_front_porch;
itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
itp.border_clr = pinfo->lcdc.border_clr;
itp.underflow_clr = pinfo->lcdc.underflow_clr;
itp.hsync_skew = pinfo->lcdc.hsync_skew;
mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
itp.width + itp.h_front_porch;
vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
itp.height + itp.v_front_porch;
hsync_start_x =
itp.hsync_pulse_width +
itp.h_back_porch;
hsync_end_x =
hsync_period - itp.h_front_porch - 1;
display_vstart = (itp.vsync_pulse_width +
itp.v_back_porch)
* hsync_period + itp.hsync_skew;
display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ itp.hsync_skew - 1;
if (intf_base == MDP_INTF_0_BASE) { /* eDP */
display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
display_vend -= itp.h_front_porch;
}
hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off);
writel(display_vstart, MDP_DISPLAY_V_START_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
writel(display_vend, MDP_DISPLAY_V_END_F0 +
mdss_mdp_intf_off);
writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
if (intf_base == MDP_INTF_0_BASE) /* eDP */
writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
else
writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
return NO_ERROR;
}
int mdp_edp_on(void)
{
writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
return NO_ERROR;
}
static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
uint32_t adjust_xres = 0;
uint32_t upper = 0, lower = 0;
struct lcdc_panel_info *lcdc = NULL;
struct intf_timing_params itp = {0};
if (pinfo == NULL)
return;
lcdc = &(pinfo->lcdc);
if (lcdc == NULL)
return;
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display) {
adjust_xres /= 2;
if (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset())) {
if (pinfo->lcdc.pipe_swap) {
lower |= BIT(4);
upper |= BIT(8);
} else {
lower |= BIT(8);
upper |= BIT(4);
}
writel(lower, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL);
writel(upper, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL);
writel(0x1, MDP_REG_SPLIT_DISPLAY_EN);
}
}
if (pinfo->lcdc.dst_split && (intf_base == (MDP_INTF_1_BASE + mdss_mdp_intf_offset()))) {
uint32_t ppb_offset = mdss_mdp_get_ppb_offset();
writel(BIT(16), REG_MDP(ppb_offset + 0x4)); /* MMSS_MDP_PPB0_CNTL */
writel(BIT(5), REG_MDP(ppb_offset)); /* MMSS_MDP_PPB0_CONFIG */
}
if (!pinfo->fbc.enabled || !pinfo->fbc.comp_ratio)
pinfo->fbc.comp_ratio = 1;
itp.xres = (adjust_xres / pinfo->fbc.comp_ratio);
itp.yres = pinfo->yres;
itp.width =((adjust_xres + pinfo->lcdc.xres_pad) / pinfo->fbc.comp_ratio);
itp.height = pinfo->yres + pinfo->lcdc.yres_pad;
itp.h_back_porch = pinfo->lcdc.h_back_porch;
itp.h_front_porch = pinfo->lcdc.h_front_porch;
itp.v_back_porch = pinfo->lcdc.v_back_porch;
itp.v_front_porch = pinfo->lcdc.v_front_porch;
itp.hsync_pulse_width = pinfo->lcdc.h_pulse_width;
itp.vsync_pulse_width = pinfo->lcdc.v_pulse_width;
itp.border_clr = pinfo->lcdc.border_clr;
itp.underflow_clr = pinfo->lcdc.underflow_clr;
itp.hsync_skew = pinfo->lcdc.hsync_skew;
hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
itp.width + itp.h_front_porch;
vsync_period = itp.vsync_pulse_width + itp.v_back_porch +
itp.height + itp.v_front_porch;
hsync_start_x =
itp.hsync_pulse_width +
itp.h_back_porch;
hsync_end_x =
hsync_period - itp.h_front_porch - 1;
display_vstart = (itp.vsync_pulse_width +
itp.v_back_porch)
* hsync_period + itp.hsync_skew;
display_vend = ((vsync_period - itp.v_front_porch) * hsync_period)
+ itp.hsync_skew - 1;
if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) { /* eDP */
display_vstart += itp.hsync_pulse_width + itp.h_back_porch;
display_vend -= itp.h_front_porch;
}
hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
writel(hsync_ctl, MDP_HSYNC_CTL + intf_base);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
intf_base);
writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base);
writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
intf_base);
writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base);
writel(display_hctl, MDP_DISPLAY_HCTL + intf_base);
writel(display_vstart, MDP_DISPLAY_V_START_F0 +
intf_base);
writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base);
writel(display_vend, MDP_DISPLAY_V_END_F0 +
intf_base);
writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base);
writel(0x00, MDP_ACTIVE_HCTL + intf_base);
writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base);
writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base);
writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base);
writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base);
writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base);
if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */
writel(0x212A, MDP_PANEL_FORMAT + intf_base);
else
writel(0x213F, MDP_PANEL_FORMAT + intf_base);
}
