static void dsp32c_reset(void *param)
{
struct dsp32_config *config = param;
/* copy in config data */
if (config)
dsp32.output_pins_changed = config->output_pins_changed;
/* reset goes to 0 */
dsp32.PC = 0;
memory_set_opbase(dsp32.PC);
/* clear some registers */
dsp32.pcw &= 0x03ff;
update_pcr(dsp32.pcr & PCR_RESET);
dsp32.esr = 0;
dsp32.emr = 0xffff;
/* initialize fixed registers */
dsp32.R0 = dsp32.R0_ALT = 0;
dsp32.RMM = -1;
dsp32.RPP = 1;
dsp32.A_0 = 0.0;
dsp32.A_1 = 1.0;
/* init internal stuff */
dsp32.abufcycle[0] = dsp32.abufcycle[1] = dsp32.abufcycle[2] = dsp32.abufcycle[3] = 12345678;
dsp32.mbufaddr[0] = dsp32.mbufaddr[1] = dsp32.mbufaddr[2] = dsp32.mbufaddr[3] = 1;
}
void cpunum_set_opbase(int cpunum, unsigned val)
{
VERIFY_CPUNUM(cpunum_set_opbase);
cpuintrf_push_context(cpunum);
memory_set_opbase(val);
cpuintrf_pop_context();
}
void cpunum_reset(int cpunum)
{
VERIFY_CPUNUM(cpunum_reset);
cpuintrf_push_context(cpunum);
memory_set_opbase(0);
(*cpu[cpunum].intf.reset)();
cpuintrf_pop_context();
}
static void dsp56k_set_context(void *src)
{
/* copy the context */
if (src)
dsp56k = *(dsp56k_regs *)src;
memory_set_opbase(PC);
/* check for IRQs */
check_irqs();
}
int cpunum_execute(int cpunum, int cycles)
{
int ran;
VERIFY_CPUNUM(cpunum_execute);
cpuintrf_push_context(cpunum);
executingcpu = cpunum;
memory_set_opbase(activecpu_get_physical_pc_byte());
ran = (*cpu[cpunum].intf.execute)(cycles);
executingcpu = -1;
cpuintrf_pop_context();
return ran;
}
void activecpu_set_opbase(unsigned val)
{
VERIFY_ACTIVECPU(activecpu_set_opbase);
memory_set_opbase(val);
}
void activecpu_reset_banking(void)
{
VERIFY_ACTIVECPU(activecpu_reset_banking);
memory_set_opbase(activecpu_get_physical_pc_byte());
}
// Page 101 (7-25) in the Family Manual
static void dsp56k_reset(void)
{
if (dsp56k.config == NULL)
{
memory_set_opbase(PC);
// Handle internal stuff
dsp56k.interrupt_cycles = 0;
// Internal peripheral devices are reset, and pins revert to general I/O pins
// Modifier registers are set
M0 = M1 = M2 = M3 = 0xffff;
// BCR is set - the really slow bootup mode & the Bus State status bit high (0x4xxx)
//BCR = 0x43ff;
// Stack pointer is cleared
SP = 0x00; // The docs say nothing about ufBIT & seBIT, but this should be right
// Documentation says 'MR' is setup, but it really means 'SR' is setup
SR = 0x0300; // Only the Interrupt mask bits of the Status Register are set upon reset
// !!! GO THROUGH AND GET ALL THESE RIGHT SOMEDAY !!!
HSR = 0x0000;
SET_htdeBIT();
dsp56k_reset_HI();
OMR = 0x00; // All is cleared, except for the IRQ lines below
IPR = 0x00;
dsp56k.repFlag = 0; // Certainly not repeating to start
dsp56k.repAddr = 0x0000; // Reset the address too...
// Manipulate everything you need to for the ports (!! maybe these will be callbacks someday !!)...
data_write_word_16le(0xffc0, 0x0000); // Sets Port B Control Register to general I/O
data_write_word_16le(0xffc2, 0x0000); // Sets Port B Data Direction Register as input
data_write_word_16le(0xffc1, 0x0000); // Sets Port C Control Register to general I/O
data_write_word_16le(0xffc3, 0x0000); // Sets Port C Data Direction Register as input
// Now that we're leaving, set ma, mb, and mc from MODA, MODB, and MODC lines
// I believe polygonet sets everyone to mode 0... The following reflects this...
CLEAR_maBIT();
CLEAR_mbBIT();
// switch bootup sequence based on chip operating mode
switch((mbBIT << 1) | maBIT)
{
// [Special Bootstrap 1] Bootstrap from an external byte-wide memory located at P:$c000
case 0x0:
PC = 0x0000; // 0x0030; // 0x0032; // 0x002e; // 0x0000; // 0x002c;
break;
// [Special Bootstrap 2] Bootstrap from the Host port or SSI0
case 0x1:
PC = 0x0000;
break;
// [Normal Expanded] Internal PRAM enabled; External reset at P:$e000
case 0x2:
PC = 0xe000;
break;
// [Development Expanded] Int. program memory disabled; Ext. reset at P:$0000
case 0x3:
PC = 0x0000;
break;
}
}
else
{
PC = *((UINT16*)dsp56k.config);
}
}
offs_t activecpu_dasm(char *buffer, offs_t pc)
{
VERIFY_ACTIVECPU(activecpu_dasm);
/* allow overrides */
if (cpu_dasm_override)
{
offs_t result = cpu_dasm_override(activecpu, buffer, pc);
if (result)
return result;
}
/* if there's no old-style assembler, do some work to make this call work with the new one */
if (!cpu[activecpu].intf.disassemble)
{
int dbwidth = activecpu_databus_width(ADDRESS_SPACE_PROGRAM);
int maxbytes = activecpu_max_instruction_bytes();
int endianness = activecpu_endianness();
UINT8 opbuf[64], argbuf[64];
int xorval = 0;
int numbytes;
/* determine the XOR to get the bytes in order */
switch (dbwidth)
{
case 8: xorval = 0; break;
case 16: xorval = (endianness == CPU_IS_LE) ? BYTE_XOR_LE(0) : BYTE_XOR_BE(0); break;
case 32: xorval = (endianness == CPU_IS_LE) ? BYTE4_XOR_LE(0) : BYTE4_XOR_BE(0); break;
case 64: xorval = (endianness == CPU_IS_LE) ? BYTE8_XOR_LE(0) : BYTE8_XOR_BE(0); break;
}
/* fetch the bytes up to the maximum */
memset(opbuf, 0xff, sizeof(opbuf));
memset(argbuf, 0xff, sizeof(argbuf));
for (numbytes = 0; numbytes < maxbytes; numbytes++)
{
offs_t physpc = pc + numbytes;
const UINT8 *ptr;
/* translate the address, set the opcode base, and apply the byte xor */
if (!cpu[activecpu].intf.translate || (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, &physpc))
{
memory_set_opbase(physpc);
physpc ^= xorval;
/* get pointer to data */
ptr = memory_get_op_ptr(cpu_getactivecpu(), physpc, 0);
if (ptr)
{
opbuf[numbytes] = *ptr;
ptr = memory_get_op_ptr(cpu_getactivecpu(), physpc, 1);
if (ptr)
argbuf[numbytes] = *ptr;
else
argbuf[numbytes] = opbuf[numbytes];
}
}
}
return activecpu_dasm_new(buffer, pc, opbuf, argbuf, maxbytes);
}
return (*cpu[activecpu].intf.disassemble)(buffer, pc);
}